Semiconductor Memory
Part of Data Storage
How transistors and capacitors store bits in silicon — from fast SRAM registers to dense DRAM and persistent ROM.
Why This Matters
Semiconductor memory is what makes modern computers fast. The gap between processor speed and mechanical storage speed — billions of operations per second versus thousands for disk access — would make computing practically useless without a fast memory buffer. Semiconductor memory fills that role. Static RAM responds in nanoseconds. Dynamic RAM packs gigabytes into a single chip.
For rebuilders, semiconductor memory occupies a paradoxical position. It is easy to use (plug in chips, wire up address and data buses) but nearly impossible to manufacture from scratch. Silicon chip fabrication requires ultra-clean rooms, photolithography equipment, and precision chemical processes that are far beyond any near-term rebuild scenario.
The practical strategy is clear: use existing semiconductor memory as long as it works, understand it well enough to diagnose failures and find substitutes, and plan storage systems so that critical data persists to non-semiconductor media when chips eventually fail.
Understanding semiconductor memory also helps you understand what you cannot do: designing a system around large amounts of DRAM when no DRAM is available is futile. Understanding the alternatives (core memory, drum storage) lets you design systems that work with what you have.
Transistor-Based Storage: The Core Concept
All semiconductor memory stores bits as physical states of transistor-based circuits. A transistor can be in one of two states — conducting (on) or non-conducting (off) — and this binary state maps directly to a 1-bit or 0-bit.
The challenge is making this state stable, reading it accurately, and writing new states reliably — all while fitting hundreds of millions of cells onto a square centimeter of silicon.
Three main approaches achieve this:
- Cross-coupled transistor pairs (SRAM): Two inverters in a feedback loop lock into one of two stable states.
- Charge stored on a capacitor (DRAM): A tiny charge or absence of charge represents 0 or 1, but it leaks and must be refreshed.
- Charge trapped in an insulated gate (Flash/EEPROM): Long-term storage — no refresh needed, but writes are slow and limited in number.
SRAM: Speed at a Cost
Static RAM uses a bistable latch — two cross-coupled CMOS inverters — as its storage element. Each inverter output drives the other inverter’s input. Once set to one state, the circuit remains in that state as long as power is applied, with no refresh required.
Circuit: A minimal SRAM cell consists of 4 transistors (the two inverters) plus 2 access transistors (to select the cell for reading or writing). Total: 6 transistors per bit. This is the classic 6T SRAM cell used in virtually all modern SRAM products.
Access time: 1–5 nanoseconds for modern SRAM; 10–50 ns for older chips. This speed arises because reading simply senses which of two stable voltage levels the cell is holding — no charge accumulation or refresh is needed.
Density: 6 transistors per bit is far more than DRAM’s 1 transistor + 1 capacitor. SRAM density is approximately 4–8× lower than DRAM of the same generation. This makes SRAM too expensive for main memory (gigabytes would be prohibitively costly) but ideal for CPU cache (megabytes are affordable).
Power consumption: SRAM consumes power only when switching states. A static SRAM cell holding a value draws only leakage current — very low in CMOS. This makes SRAM suitable for battery-backed applications: an SRAM chip with a lithium cell can retain its data for years without external power.
Identifying SRAM chips: Part numbers often begin with 61 (e.g., 6116 = 2K×8 SRAM, 6264 = 8K×8 SRAM, 62256 = 32K×8 SRAM). Pinout is standardized: address pins labeled A0–An, data pins D0–D7, chip select (/CS), output enable (/OE), write enable (/WE).
DRAM: Density at the Cost of Complexity
Dynamic RAM uses a single transistor plus a single capacitor per bit. The transistor acts as a switch; when selected, it connects the capacitor to the data line. If the capacitor is charged, it represents a 1; if discharged, a 0.
The refresh problem: A capacitor slowly leaks charge — in DRAM, the charge leaks completely within 1–100 milliseconds depending on temperature. To prevent data loss, every row of the DRAM array must be read and rewritten (refreshed) at least once per refresh period. This is called the refresh cycle. All DRAM controllers include refresh timing logic that automatically initiates a row refresh every few microseconds.
Density advantage: One transistor + one capacitor per bit requires far less silicon area than six transistors. This is why DRAM achieves densities of gigabytes per chip while SRAM tops out at megabytes per chip.
Access time: Slower than SRAM (50–100 ns for typical DRAM, down to 10–20 ns for DDR SDRAM with burst access), but fast enough for main memory.
Organization: DRAM is organized as a matrix of rows and columns. To read a specific bit, you select a row (raising the row address strobe, RAS#) which activates an entire row of cells and dumps their charge onto sense amplifiers. Then you select a column (raising the column address strobe, CAS#) to read or write the specific bit. Modern SDRAM (synchronous DRAM) adds a clock and burst-access modes for higher bandwidth.
Identifying DRAM chips: Older 1-bit-wide chips include 4116 (16K×1), 4164 (64K×1), 41256 (256K×1). 8-bit-wide chips are more recent: 41464 (64K×4), 44256 (256K×4). Modern DIMMs (Dual Inline Memory Modules) contain 8 DRAM chips of increasing density.
ROM: Permanent Semiconductor Storage
Read-Only Memory stores bits permanently, without requiring power. The data is encoded into the chip’s physical structure and cannot be erased or overwritten in normal operation.
Mask ROM: The data is “baked in” during the chip manufacturing process, encoded in the pattern of metal connections or implanted dopants. Fast, cheap for large quantities, but requires a new mask (tooling) to change the data. Used for factory-programmed microcontroller firmware, character generation ROMs, and game cartridges.
PROM (Programmable ROM): Shipped from the factory with all bits 1 (or all 0). The user programs it by blowing fusible links (or anti-fuse elements) for specific bits, permanently changing them. One-time programmable — once a bit is written, it cannot be restored.
EPROM (Erasable PROM): Uses a floating-gate transistor structure where charge can be trapped in an insulated gate. Programmed by applying high voltage (typically 12.5V) to inject electrons onto the floating gate. Erased by exposing the chip to UV light (through the quartz window visible on the top of the chip package) for 15–60 minutes, which gives the trapped electrons enough energy to escape. Reprogrammable hundreds of times.
EEPROM (Electrically Erasable PROM): Similar floating-gate structure but allows both programming and erasing with normal voltages (5V or 3.3V), without UV light. Can be erased and reprogrammed byte by byte, in-circuit. Slower and more expensive than EPROM but far more convenient.
Flash memory: An EEPROM variant optimized for high density by requiring block erasing (entire sectors, typically 4 KB–64 KB, must be erased before individual bytes can be rewritten). Used in USB drives, SSDs, memory cards. Very high density (hundreds of gigabytes per chip) but limited write endurance (typically 1,000–100,000 erase cycles per block).
Practical Use in a Rebuild System
Working with available chips: In a scenario where you have access to salvaged electronics, the most likely semiconductor memory to find is:
- SRAM in small sizes (6116, 6264, 62256) from legacy embedded systems, game cartridges, old computers
- DRAM in larger sizes as SIMM or DIMM modules from scrapped PCs
- EPROM (27Cxxx series) from embedded systems
- EEPROM (28Cxxx, 24Cxxx series) from device configuration storage
Building a memory board: A simple 32 KB SRAM system using a 62256 chip requires: the chip itself, decoding logic to assert /CS when the address is in the chip’s range, and connection to the CPU’s address, data, and control buses. With a 74HC138 address decoder and a few bypass capacitors, this is a half-day wiring project.
Battery backup: A lithium coin cell (3V, CR2032 type) in series with a Schottky diode can power an SRAM chip when main power is off, preserving data indefinitely. Total backup current for a 32 KB SRAM in standby is typically 1–10 microamps, giving years of backup on a single coin cell.
When chips fail: SRAM and DRAM chips fail in characteristic patterns. Stuck address lines cause systematic patterns (half the memory is inaccessible or reads wrong addresses). Stuck data lines cause specific bit positions to read as always-0 or always-1. Cell failures cause individual bits to fail. Pattern memory tests (writing and reading-back known patterns) can diagnose which type of failure has occurred and whether the chip should be replaced or (if a simple bit failure) partially avoided through software memory mapping.