Dynamic RAM (DRAM)

Part of Data Storage

Capacitor-based memory cells that pack enormous density at the cost of continuous refresh — the foundation of all main memory.

Why This Matters

Dynamic RAM makes large main memory affordable. By storing each bit as a charge on a tiny capacitor accessed through a single transistor (instead of the six transistors of SRAM), DRAM achieves four to eight times higher density per unit area. This density difference is what puts gigabytes of RAM into laptops rather than hundreds of kilobytes.

The cost of this density is complexity: capacitors leak. A DRAM cell loses its charge and forgets its data within milliseconds. To prevent this, every row of the memory array must be periodically refreshed — read and rewritten before the charge leaks too far. This refresh requirement drives the entire DRAM controller design and creates a unique set of pitfalls for system builders.

For rebuilders, DRAM chips (and especially DRAM modules — SIMMs and DIMMs) represent the most abundant source of salvageable large memory. A single DDR SDRAM DIMM from a scrapped desktop computer provides gigabytes of working memory. Understanding how to interface and refresh DRAM correctly lets you use this abundant resource.

The 1T1C Cell

A DRAM cell consists of one transistor (the access transistor) and one capacitor (the storage capacitor), hence the name 1T1C cell.

Storage mechanism: A charge on the capacitor represents a 1-bit; the absence of charge (discharged capacitor) represents a 0-bit. In practice, a full capacitor holds the supply voltage (Vcc, typically 1.5–3.3V); an empty capacitor holds approximately 0V.

The leakage problem: Real capacitors are not perfect. Charge leaks slowly through the oxide insulation surrounding the capacitor plate. DRAM capacitors lose half their charge in approximately 10–100 milliseconds at room temperature. Higher temperatures accelerate leakage (roughly doubling for every 10°C increase). Without intervention, every 1-bit would become a 0-bit within a second.

Refresh: The DRAM controller must read every row of the array at least once per refresh interval (typically 64 ms for modern DRAM, specified in the datasheet as tREF). Reading a row causes the sense amplifiers to detect the partially discharged capacitors, amplify the signals to full levels, and write the amplified signal back to the cells — restoring the charge to full level. This is “refresh.”

A DRAM with 8,192 rows must complete one refresh cycle every 64 ms / 8,192 rows = 7.8 microseconds. Modern DRAM controllers issue refresh commands automatically; older controllers (and any custom controller you design) must generate these refresh pulses in hardware.

Row-Column Addressing

DRAM uses a multiplexed address scheme to reduce pin count. Instead of providing a full address in one step, DRAM accepts a row address and then a column address through the same address pins.

RAS# (Row Address Strobe): When asserted low, the DRAM latches the current address pins as the row address. Internally, this activates the entire row — all cells in the row are read out by the sense amplifiers and held ready.

CAS# (Column Address Strobe): After RAS# has been asserted, CAS# latches the current address pins as the column address. The sense amplifier output for the selected column is driven onto the data output pin.

Advantage: By multiplexing row and column addresses, a chip with 12 address pins can address 2^24 = 16 million cells (12 row bits × 12 column bits), requiring only 12 pins instead of 24. This halves the pin count, reducing package size and cost.

Page mode: If RAS# remains asserted (row stays open), multiple CAS# pulses can read different columns from the same row without re-issuing RAS#. This is “page mode” access and is significantly faster than RAS# cycling for sequential access. Modern SDRAM (synchronous DRAM) and DDR (double data rate) SDRAM extend this concept with burst access modes.

DRAM Generations and Timing

DRAM has evolved through several generations, each improving timing parameters and bandwidth:

Asynchronous DRAM (1970s–1990s): The original DRAM interface, controlled by RAS# and CAS# pulses with no clock. The controller generates these signals using discrete timing circuits. Common chips: 4116 (16K×1, 5V/-12V/+12V — three supply voltages), 4164 (64K×1, 5V only), 41256 (256K×1), 44256 (256K×4).

FPM DRAM (Fast Page Mode, 1980s–1990s): Asynchronous with faster column access within an open row. Used in 30-pin and 72-pin SIMMs. Access time 60–80 ns.

EDO DRAM (Extended Data Out, early 1990s): Output data remains valid longer after CAS# de-assertion, allowing overlap of adjacent accesses. Slightly faster than FPM.

SDRAM (Synchronous DRAM, mid-1990s onward): Synchronizes all operations to a clock signal. Allows internal pipelining. 168-pin DIMMs. Data rates 66–133 MHz.

DDR SDRAM (Double Data Rate, 2000s): Transfers data on both rising and falling edges of the clock, doubling bandwidth. DDR through DDR5 generations, each doubling bandwidth again. 184-pin to 288-pin DIMMs.

For a rebuilder using salvaged memory, older asynchronous DRAM is easier to control (no complex clock timing), while SDRAM and DDR SDRAM are more abundant (from more recent scrapped equipment) but require synchronous controllers, usually a microcontroller or FPGA with sufficient speed.

Building a DRAM Controller

A functional DRAM controller must implement:

Initialization: After power-up, most DRAM requires a specific initialization sequence (several hundred microseconds of power stability, followed by multiple refresh cycles) before it accepts data operations.

Refresh timing: A hardware timer (or software interrupt) must trigger a row refresh cycle every tREF/numRows microseconds. This cannot be skipped — missing even a single refresh cycle at elevated temperature may corrupt data in the rows that went too long without refresh.

Access arbitration: The refresh controller and the CPU/bus controller both want access to the DRAM. The arbitration logic grants access to the refresh request (which is time-critical) and stalls the CPU briefly (~100 ns per refresh cycle).

RAS/CAS timing: A state machine or programmable timer must generate the RAS#, CAS#, /WE, and address multiplexing signals with correct timing. Violating tRAS (minimum time RAS# must be asserted), tRCD (time from RAS# to first CAS#), or tRC (minimum time between successive RAS# assertions) causes data corruption or chip damage.

Minimum viable DRAM controller for asynchronous 41256 chips:

• 74HC574 octal flip-flop to latch row address vs. column address on the same address lines
• 555 timer or small counter to generate periodic refresh pulses
• Small PAL (programmable array logic) or CPLD to implement RAS/CAS sequencing
• Total chip count: 5–8 ICs

Diagnosing and Testing DRAM

DRAM failures manifest in characteristic patterns:

Random bit errors: Single cells failing intermittently, often worse at elevated temperature. Run a long-duration memory test (write, read back, compare) and note which addresses fail. If failures cluster at specific rows, the entire chip may need replacement. If failures cluster at specific bit positions (always bit 3 is wrong regardless of address), suspect the data bus, not the chip.

Address line failure: An open or stuck address line causes half the memory to alias to the same locations. Manifests as every pair of addresses (X and X XOR 2^n for the stuck bit n) reading the same value.

Stuck data pin: One bit of every address always reads the same value. Check the data bus wiring and pin connection before concluding the chip is faulty.

Refresh failure: If the refresh circuit fails, data corruption starts within 100 ms and progresses to complete garbage. Distinguish from chip failure by: restoring known-good data, cutting power briefly (to reset all cells to undefined), and testing again immediately after power-up when cells still have charge. Good refresh-failed cells will read correctly immediately after power-up but corrupt within seconds.

Temperature sensitivity: DRAM that works cold but fails when the system warms up typically has borderline timing margins or elevated leakage due to marginal capacitor oxide quality. Replace affected chips if the design cannot be modified to reduce operating temperature.