Static RAM (SRAM)

Part of Data Storage

Flip-flop based memory that holds bits as long as power is applied — fast, reliable, and essential for CPU registers and cache.

Why This Matters

Static RAM is the fastest, simplest semiconductor memory. Unlike DRAM, it requires no refresh cycle, no complex timing, and no external capacitors. You write a value; it stays there until you write again or remove power. This simplicity makes SRAM the preferred choice for CPU registers, cache, and any small buffer where speed and reliability matter more than cost per byte.

For rebuilders working with salvaged electronics, SRAM chips are among the easiest memory technologies to work with. They use simple parallel interfaces, tolerate slow and asynchronous access, and are available in a wide range of sizes from dozens of legacy embedded systems, game cartridges, vintage computers, and industrial equipment. A single 62256 chip provides 32 kilobytes — enough for the working memory of many useful programs.

Understanding SRAM means understanding the bistable latch: a circuit with two stable states that you can read and write at will. This concept scales from a single transistor pair to billion-transistor cache arrays.

The 6T SRAM Cell

The standard SRAM storage cell uses six transistors arranged as two cross-coupled CMOS inverters plus two access transistors.

The bistable latch: Two CMOS inverters are connected back-to-back: the output of inverter 1 drives the input of inverter 2, and the output of inverter 2 drives the input of inverter 1. This creates a feedback loop with two stable states:

• State 0: output of inverter 1 is low (0V), which makes inverter 2’s input low, which makes its output high (Vcc), which makes inverter 1’s input high, which makes its output low. Stable.
• State 1: all signals flipped. Also stable.

Any random perturbation that momentarily pushes one node slightly will be amplified by the feedback and pulled back to the nearest stable state. This is what makes SRAM “static” — it actively maintains its state.

The access transistors: Two NMOS transistors connect the latch’s internal nodes (Q and Q-bar) to the bit lines (BL and BL-bar). When the word line (WL) is asserted high, both access transistors turn on, connecting the latch to the bit lines.

Reading: Before a read, the sense amplifier pre-charges both bit lines to Vcc/2. When WL is asserted, the latch is connected to the bit lines. The stronger pull of the latch (toward Vcc or GND on the two sides) slightly differentiates the two bit lines. The sense amplifier detects which bit line is being pulled lower and amplifies this tiny difference into a full-swing output. This differential sense approach allows very fast reads even with small (and thus fast) memory cells.

Writing: The write driver forces one bit line high and the other low with strong drive capability. When WL is asserted, the forced bit lines overwhelm the latch’s feedback and flip it to the desired state. The latch then holds this new state after WL is de-asserted.

Standard SRAM Chip Interfaces

Most parallel SRAM chips use a standard interface regardless of manufacturer:

Address pins (A0–An): Select which memory location to access. A chip with 2^n address pins has 2^n distinct locations. The 62256 has 15 address pins (A0–A14), giving 2^15 = 32,768 locations.

Data pins (D0–D7 or DQ0–DQ7): Carry the data being read or written. Most modern SRAM chips are 8 bits (1 byte) wide.

Chip Select (/CS or /CE): When asserted low, enables the chip. When high, the chip ignores all other signals and puts its data pins in high-impedance state. Multiple chips can share address and data buses using different /CS signals to select one chip at a time.

Output Enable (/OE): Controls whether the chip drives the data bus. Assert low to enable the data outputs during a read. Keep high during writes (the CPU or write driver should drive the bus, not the chip).

Write Enable (/WE): Assert low to perform a write operation. The data on the D pins is stored at the selected address on the rising edge of /WE.

Typical read cycle: Set address → assert /CS → assert /OE → wait for access time (e.g., 70 ns for a 62256-70) → read data → de-assert /OE → de-assert /CS.

Typical write cycle: Set address → set data → assert /CS → assert /WE → wait for write pulse width (e.g., 40 ns) → de-assert /WE → de-assert /CS.

These timing requirements must be respected. Violating them causes metastability (undefined outputs) or corrupted writes. For slow microcontrollers (1–10 MHz), meeting these timings is trivial — a 70 ns chip is fast enough for a 10 MHz (100 ns cycle) processor with no wait states.

Battery Backup: Non-Volatile SRAM

One powerful trick with SRAM: add a battery to make it non-volatile. If the SRAM supply voltage is switched to a battery when main power fails, the chip continues to hold its data indefinitely (at very low standby current) until main power is restored.

Implementation: Use a small lithium coin cell (CR2032, 3V) in series with a Schottky diode. Connect the other side of the diode to the SRAM’s Vcc pin. Also connect the main supply through a Schottky diode to the same Vcc pin. The Schottky diodes prevent the main supply and battery from fighting each other: whichever is higher wins.

When main power is present, it provides 5V minus one Schottky drop (~0.3V) = 4.7V to the SRAM — fully operational.

When main power is removed, the SRAM voltage would fall below battery voltage. The battery then provides 3V minus one Schottky drop = 2.7V — enough for most SRAM chips to maintain data (minimum operating voltage for data retention is typically 2V or less).

Current consumption: SRAM chips in standby typically draw 1–50 microamps. A CR2032 cell holds 225 mAh. At 10 microamps standby current: 225,000 microamp-hours / 10 microamps = 22,500 hours ≈ 2.5 years of data retention.

This makes battery-backed SRAM a simple form of non-volatile storage: no file system, no seek time, no wear. Just set an address, write a value, and it is there when you come back — even after months with no power. Used in real-time clocks, machine configuration storage, and embedded system state machines for decades.

SRAM in a Practical Build

Small standalone systems: For a minimal 8-bit computer (6502, Z80, 8085 processor), a 62256 (32 KB) or 62512 (64 KB) chip provides all the working RAM needed. Wire up the address and data buses directly between CPU and SRAM. Connect /CS to the address decoder output for the RAM’s address range. Add a 100 nF ceramic bypass capacitor between Vcc and GND as close to the chip as possible.

Organized layout: Place SRAM chips at specific base addresses (e.g., starting at address 0x0000). Programs compiled for this memory map will work immediately without runtime address configuration.

Testing a SRAM chip: Write a walking-ones pattern (write 0x01 to location 0, 0x02 to location 1, 0x04 to location 2, etc.) and read it back. Errors indicate stuck data or address lines. Write alternating 0xAA and 0x55 patterns and read back — this checks all bit patterns in all cells. A chip that passes both tests is almost certainly good.

Common failure modes: Address pin stuck (every address decodes to only two locations), data pin stuck high or low (one bit always reads wrong), single cell failure (one specific address always reads wrong).

Sourcing: 62256 (32 KB×8), 62128 (16 KB×8), and 6116 (2 KB×8) chips are common in vintage computers, arcade game boards, BIOS expansion cards, and early embedded systems. All are pin-for-pin compatible across manufacturers (Hitachi, Samsung, Alliance, IDT, Cypress). Any chip with the correct part number will work in the same socket.