Memory Systems

5 min read

Parent
💻
Basic Computing
Architecture, logic, memory
Current
💾
Memory Systems
Storing data
Sub-Topics
🔄
Flip-Flops
SR latch, D flip-flop
📦
Registers
Parallel and shift registers
🧲
Core Memory
Ferrite core threading

Memory Systems

Part of Basic Computing

Memory systems store programs and data for the processor — the hierarchy from fast registers through RAM to persistent storage determines how much a computer can hold and how quickly it can work.

Why This Matters

Memory is where programs live. Without sufficient, reliable memory, even a perfect processor is useless — it has nowhere to store instructions or data. Memory design involves fundamental tradeoffs: speed vs. capacity vs. cost vs. power vs. volatility (does data survive power loss?).

Understanding memory systems allows a builder to select appropriate technology for each purpose in a computing system: fast static RAM for small working buffers, larger dynamic RAM for main memory, ROM for boot firmware, and magnetic or optical storage for permanent archives.

The memory hierarchy is also the key to understanding computer performance: most programs exhibit locality (they access the same addresses repeatedly), so small fast memory that captures recently accessed data dramatically improves effective performance beyond what the main memory speed suggests.

ROM: Read-Only Memory

ROM stores permanent data that should survive power loss. The processor can read from ROM but not write to it (during normal operation). Used for boot firmware, character generator tables, lookup tables, and fixed programs.

Mask ROM: programmed during manufacture by selectively connecting or disconnecting transistors at each bit position. Permanent, cannot be changed. Appropriate only when the program is finalized and large production volumes justify custom fabrication costs.

PROM (Programmable ROM): one-time programmable. Each bit position contains a fusible link; programming burns (blows) selected fuses, permanently writing the data. Cannot be erased or reprogrammed. Used for small production runs or prototyping.

EPROM (Erasable Programmable ROM): the 27xx series (2716 = 2K×8, 2764 = 8K×8, 27256 = 32K×8). Programmed by applying high voltage (12.5V) to address and data lines, then allowing UV light to erase (the transparent quartz window on the IC top allows UV penetration). Erasing takes 20–30 minutes under UV light at 254 nm (short-wave UV lamp). Suitable for development: program, test, UV-erase, reprogram.

EEPROM/Flash: electrically erasable, reprogrammable. 28Cxx series (28C64, 28C256). No UV needed — erase with electrical signal. More convenient than EPROM. Flash memory (EEPROMs with block erase) is what modern computers use for firmware (BIOS chips).

For a hand-built system: use 28C256 (32K×8, 5V, 150 ns access time). Program using a dedicated programmer (Willem programmer or equivalent), or a microcontroller-based programmer if no commercial programmer is available.

SRAM: Static RAM

SRAM stores data in D-latch or flip-flop cells. Data is retained as long as power is applied. Extremely fast (10–70 ns access time). Higher power than DRAM. Used for CPU cache, small working buffers, register files.

Pinout of a typical 32K×8 SRAM (62256 or HM62256):

  • A0–A14: 15 address inputs (2^15 = 32,768 locations)
  • D0–D7: 8 data I/O lines (bidirectional)
  • CE_bar: chip enable (active low)
  • OE_bar: output enable (active low, for reads)
  • WE_bar: write enable (active low, for writes)

Read cycle: assert CE_bar low, assert OE_bar low, place address on A0–A14. After access time (typically 70 ns), data appears on D0–D7.

Write cycle: assert CE_bar low, assert WE_bar low, place address and data. After setup time, deassert WE_bar — the data is latched.

For a hand-built computer with 64K address space: use two 32K×8 SRAMs (one covering 0x0000–0x7FFF, the other 0x8000–0xFFFF) with CE_bar driven by address bit A15. This provides 64KB of RAM, replacing most of the address space. Reserve the top few kilobytes (by modifying address decoding) for ROM and I/O.

DRAM: Dynamic RAM

DRAM stores each bit in a capacitor-transistor cell. Extremely compact (1 transistor per bit vs. 6 for SRAM). The capacitor leaks charge, so the memory must be refreshed (rewritten) every 1–16 ms, adding significant interface complexity.

DRAM is used for main memory in large systems (megabytes to gigabytes) where density is critical. For small hand-built systems, the refresh circuitry overhead makes DRAM unattractive — use SRAM unless memory larger than a few megabytes is required.

DRAM refresh requirement: the processor or a dedicated refresh controller must periodically cycle through all rows (a 256K×1 DRAM might need 256 row refreshes every 4 ms). During refresh, the DRAM cannot be accessed. This RAS-only refresh cycle must be incorporated into the memory controller design.

Memory Map Design

The memory map assigns address ranges to RAM, ROM, and I/O. A typical 16-bit address space (64 KB) layout:

0x0000 – 0x7FFF : 32 KB RAM (user programs, data, stack)
0x8000 – 0xBFFF : 16 KB ROM (boot monitor, BIOS routines)
0xC000 – 0xFEFF : 8 KB additional RAM or expansion
0xFF00 – 0xFFFF : 256 bytes I/O space (memory-mapped peripherals)

Address decoder implementation: high-order address bits determine which device is selected. For the layout above:

  • A15=0 → RAM (0x0000–0x7FFF)
  • A15=1, A14=0 → ROM (0x8000–0xBFFF)
  • A15=1, A14=1, A8-A0 = 0xFF → I/O (0xFF00–0xFFFF)

Implement with a 74HC138 (3-to-8 decoder) driven by the top address bits. Each output drives the CE_bar pin of one memory or I/O chip.

Reset vector: the CPU starts execution at a fixed address after reset (e.g., 0x8000 for the layout above). The ROM at that address contains the boot monitor. Ensure the address decoder is correct and the ROM is programmed before powering on.