Core Memory

Part of Basic Computing

Magnetic core memory is a non-volatile, hand-constructable RAM technology that was the dominant computer memory from the 1950s through the 1970s — and can be built without semiconductor fabrication.

Why This Matters

Semiconductor RAM requires advanced fabrication facilities unavailable to early-stage civilization rebuilding efforts. Core memory, by contrast, requires only small ferrite toroids, fine wire, and careful winding. It dominated computing from ENIAC through the early years of the Apollo program precisely because it was manufacturable without exotic technology.

Core memory is also non-volatile: it retains stored data without power. Losing power does not lose the program or data. This makes it uniquely suited for reliability-critical applications where power interruptions are common.

Understanding core memory provides insight into the physical nature of information storage — how a magnetic domain encodes a bit — and demonstrates that information storage is fundamentally a physical phenomenon subject to physical manipulation and recovery.

How Core Memory Works

A ferrite toroid (small donut-shaped ring of ferrite ceramic) can be magnetized in either of two stable directions — clockwise or counterclockwise. These two states represent binary 0 and 1. Because ferrite is a hard magnetic material, it retains its magnetization indefinitely without external energy — true non-volatile storage.

Writing a bit: drive sufficient current through a wire threaded through the toroid’s center to switch its magnetization to the desired state. The required current (typically 200–400 mA depending on toroid size) generates a magnetic field strong enough to overcome coercivity and flip the domain.

Reading a bit is destructive: drive current in the “write 0” direction. If the core held a 1, the magnetic flux changes, inducing a voltage pulse on a separate sense wire also threaded through the core. If the core held a 0, no flux change occurs (already in that state), so no pulse appears. The sense pulse = was a 1; no pulse = was a 0. After reading, the core is left in state 0, so the read circuit must immediately rewrite the original value — a read-modify-write cycle.

Memory Array Organization

Cores are arranged in a 2D grid. Each core has four wires threaded through it:

• X drive wire: runs horizontally through all cores in a row
• Y drive wire: runs vertically through all cores in a column
• Sense wire: threads diagonally through the entire plane, one per plane
• Inhibit wire: also threads diagonally, allows selective write inhibit

Writing uses coincident-current selection: to write to the core at address (row=3, col=5), drive half the required current through X wire 3 AND Y wire 5 simultaneously. The core at their intersection receives the full switching current; all other cores on those lines receive only half current — insufficient to switch.

This halving reduces the required drive current per line and allows a complete NxN matrix to be addressed with only N+N = 2N drive circuits instead of N² — a huge practical advantage.

For a core plane storing 64×64 = 4,096 bits, only 128 drive circuits are needed. The sense wire detects changes in any core in the entire plane; a change on a specific location is identified by knowing which X and Y wires were driven.

Physical Construction of a Core Plane

Materials needed:

• Ferrite toroids: 1–2mm outer diameter, 0.6mm inner diameter; need thousands for useful memory
• Magnet wire: 28–36 AWG enameled copper wire
• Frame: PCB, rigid plastic, or metal grid to hold cores
• Drive electronics: transistor H-bridges or relay switches per wire

Threading process (tedious but achievable):

1. Arrange cores in a jig holding them at grid positions
2. Thread X wires first: run one wire through each core in row 0, left to right; fold back (or use new wire) for row 1; repeat for all rows
3. Thread Y wires: perpendicular to X wires, through each core in each column
4. Thread sense wire diagonally through all cores (sensing one bit per core per cycle)
5. Thread inhibit wire opposite diagonal

For a 16×16 array (256 bits), threading takes several hours. For 64×64 (4 Kbits), expect 40–80 hours of careful work. Errors (missed cores, wrong direction) cause incorrect operation; mark progress carefully and test after each row.

Drive Electronics

The drive electronics must:

1. Select which X and Y wires to drive
2. Generate precise current pulses (half-select or full-select as appropriate)
3. Detect the sense wire pulse during read
4. Control timing precisely

X and Y drivers are current-mode amplifiers, often using bipolar transistors in H-bridge configuration to drive current in either direction through each line. The magnitude is set by a current-limiting resistor: I = (Vsupply − Vsat) / R.

Sense amplifier: the induced voltage pulse during reading is small (millivolts). A differential amplifier (using an op-amp or discrete transistor diff-pair) compares the sense wire to a reference and outputs a logic level. The reference is typically set between the “full flux change” and “no flux change” voltage levels.

Timing control: a read cycle requires: (1) drive read pulse on X, Y; (2) wait for sense amp output to settle; (3) latch sense amp output; (4) drive rewrite pulse to restore original state. With relay-based drivers, this cycle takes milliseconds; with transistors, microseconds.

Testing and Calibration

Test a completed core plane by:

1. Write all zeros: drive read pulse on every address, check no sense pulse appears
2. Write a checkerboard pattern: alternate 0 and 1 at each address
3. Read back and verify each value

Common failures:

• Core not switching: insufficient drive current; reduce R in current-limiting circuit
• Adjacent cells disturbing each other: drive current too high; reduce slightly
• No sense output: sense wire threaded wrong direction (reverse and retry)
• Random errors: sense amplifier threshold set too high or low; calibrate

Core memory is slow (cycle times of 1–10 µs), power-hungry (hundreds of milliwatts), and labor-intensive to build. But it works without semiconductor fabrication, retains data through power loss, and can be repaired by rewinding individual wires — an attractive tradeoff in a resource-constrained rebuilding context.