Flip-Flops
Part of Basic Computing
Flip-flops are bistable circuits that store one bit of information, forming the foundation of registers, counters, and all sequential digital logic.
Why This Matters
Combinational logic (gates) is stateless — outputs depend only on current inputs with no memory. Flip-flops add memory to digital circuits: they store state between clock cycles and change only when explicitly triggered. Without flip-flops, there are no registers, no program counters, no CPUs.
A flip-flop is conceptually simple — two cross-coupled gates creating a stable latch — yet it is architecturally fundamental. Every bit of internal CPU state, every bit in a register file, every bit in a shift register, is stored in a flip-flop. Understanding how flip-flops work at the gate level removes the last mystery between basic logic gates and a working processor.
Flip-flops can be built from discrete transistors or logic gate ICs without any specialized components, making them achievable in early rebuilding stages.
SR Latch: The Basic Memory Element
The SR (Set-Reset) latch is the simplest bistable circuit, built from two cross-coupled NAND or NOR gates.
NAND latch (active-low inputs):
S_bar ─┐ Q
NAND ─────────┐
┌────┘ └─── NAND ─── Q_bar
│ ┌───┘
R_bar ─── NAND ──────┘
Truth table (S_bar, R_bar are active-low — 0 means asserted):
| S_bar | R_bar | Q | Q_bar | Action |
|---|---|---|---|---|
| 1 | 1 | Q | Q_bar | Hold (no change) |
| 0 | 1 | 1 | 0 | Set (Q=1) |
| 1 | 0 | 0 | 1 | Reset (Q=0) |
| 0 | 0 | * | * | Forbidden (both outputs try to be 1) |
The hold state (S_bar=R_bar=1) is what provides memory: the latch remains in its last state.
NOR latch (active-high inputs, complementary behavior): S=1 sets Q=1; R=1 resets Q=0.
The forbidden state must be avoided in practice. Circuit design ensures S and R are never simultaneously asserted, typically by using additional logic to derive S and R from a single data input and clock signal.
D Flip-Flop
The D (Data) flip-flop solves the forbidden-state problem by taking a single data input D and transferring it to output Q on the active clock edge.
D flip-flop behavior:
- Rising clock edge: Q captures the current value of D
- Between clock edges: Q holds its value regardless of D changes
Edge-triggered D flip-flop from logic gates: most practical implementations use a master-slave configuration:
- Master latch (transparent when clock = 0): captures D when CLK=0
- Slave latch (transparent when clock = 1): captures master output when CLK=1
- At the CLK 0→1 transition: master closes (stops changing), slave opens and captures the master’s value
The result: D is sampled at exactly the rising edge of CLK.
D flip-flop using 74HC74 (dual D flip-flop IC):
- Pin 2: D input
- Pin 3: CLK input
- Pin 5: Q output
- Pin 6: Q_bar output
- Additional pins: async PRESET and CLEAR (active-low, force Q=1 or Q=0 regardless of clock)
Setup time constraint: D must be stable for a minimum time (setup time, typically 5–20 ns for TTL) before the clock edge. Hold time: D must remain stable for a minimum time after the clock edge. Violations cause metastability — Q settles to an unpredictable value.
JK and T Flip-Flops
JK flip-flop: eliminates the forbidden state by defining J=K=1 as “toggle” (Q flips to its complement). J=K=0 holds, J=1 K=0 sets, J=0 K=1 resets. The JK is the most general single-bit state element.
T (Toggle) flip-flop: single input T; when T=1, Q toggles on each clock edge; when T=0, Q holds. T flip-flops chain naturally to make binary counters: each stage divides the clock frequency by 2.
Binary counter from T flip-flops (each stage drives the next stage’s clock):
- Stage 0: toggles every clock cycle → 2:1 frequency divider, bit 0
- Stage 1: toggles every 2 clock cycles → 4:1 divider, bit 1
- Stage 2: toggles every 4 clock cycles → 8:1 divider, bit 2
- Stage N: 2^(N+1):1 divider, bit N
Four stages give a 4-bit counter (0–15) that cycles through all values and rolls over. The 74HC393 contains two 4-bit binary ripple counters.
Registers Built from Flip-Flops
An N-bit register is N D flip-flops sharing a common clock signal. A parallel load register:
- N data inputs D[0]…D[N-1], each connected to one flip-flop’s D input
- One clock input CLK connected to all flip-flops
- N outputs Q[0]…Q[N-1]
On each rising CLK edge, all N data inputs are simultaneously captured. This is the basic building block of every register in a CPU.
An 8-bit register with enable: add an enable gate (AND or MUX) before each D input. When Enable=0, the flip-flop’s D input is forced to its current Q output (feedback), so the register holds. When Enable=1, the external data passes through.
Shift register: wire the Q output of each flip-flop to the D input of the next. On each clock edge, data shifts one position. A serial-in, parallel-out shift register converts serial bit streams to parallel bytes — useful for receiving serial data (keyboard, serial communication).
Practical implementation: 74HC174 (6-bit register), 74HC273 (8-bit register with common clock and clear), 74HC595 (8-bit serial-in, parallel-out shift register with output latch). These single-chip solutions replace up to 8 discrete flip-flops each, dramatically simplifying construction.