Logic Gates

Part of Basic Computing

Logic gates are the physical circuits that implement Boolean operations — translating voltage levels into binary decisions that form the foundation of all digital computing hardware.

Why This Matters

Logic gates are the atoms of digital electronics. Understanding them means understanding how computation is physically realized. A reader who grasps logic gates can follow any digital circuit’s behavior, reason about timing and signal integrity, design new circuits from Boolean specifications, and troubleshoot gate-level faults.

Logic gates are also accessible: they can be built from two transistors, a few resistors, and a power supply. The technology gap between “I understand Boolean algebra” and “I have working gates on a breadboard” is small. Once gates exist, anything computable can be built by combining them.

Historical context: the evolution from relay-based gates (1940s) to vacuum tube gates (1950s) to discrete transistor gates (late 1950s) to integrated circuits (1960s) represents successive improvements in speed, power, and density — but the Boolean logic each implements is identical.

From Transistors to Gates

A transistor is a three-terminal electronic switch. For an NPN bipolar junction transistor (BJT):

• Base (control input): small current turns the transistor on or off
• Collector: high-side current path
• Emitter: low-side current path (usually connected to ground)

When base voltage exceeds ~0.7V (forward threshold), the transistor saturates: collector-emitter resistance drops to near zero, current flows freely from collector to emitter. This is the “on” state.

When base voltage is below threshold, the transistor is off: collector-emitter acts as an open circuit.

Inverter (NOT gate) using one NPN transistor:

• Input through 10kΩ resistor to base
• 1kΩ load resistor from +5V to collector
• Emitter to ground, output at collector

Input high (5V) → transistor on → collector pulled to near 0V → output low. Input low (0V) → transistor off → collector pulled to 5V by resistor → output high.

This is logic inversion. Two such inverters in series = buffer (double inversion = no net inversion, but with current amplification at each stage).

NAND gate using two NPN transistors in series:

• Both transistors’ emitter-collector paths in series (emitter of T1 to collector of T2, T2 emitter to ground)
• Bases of T1 and T2 are inputs A and B through 10kΩ base resistors
• Load resistor from +5V to junction of T1 collector / T1 emitter-T2 collector
• Output at that same junction

Only when both A AND B are high (both transistors saturate) does the output pull low. Any other combination: output high. This is NAND(A, B).

Logic Families: TTL and CMOS

Two dominant logic families determine the electrical characteristics of gates.

TTL (Transistor-Transistor Logic):

• 5V supply
• Logic 0: 0–0.8V; Logic 1: 2.0–5V (with margin)
• Output drive: sufficient for 10 TTL loads
• Power: significant static power dissipation (milliwatts per gate)
• Speed: propagation delay 5–30 ns
• 74xx series (7400, 7486, etc.); LS (low-power Schottky) and HC variants

CMOS (Complementary Metal-Oxide Semiconductor):

• 3V–15V supply (74HC series: 2–6V)
• Logic 0: 0–0.3×Vdd; Logic 1: 0.7×Vdd – Vdd
• Very high input impedance: does not load driving circuit
• Static power: near zero (only dynamic power during switching)
• Speed: comparable to LS-TTL at 5V; slower at lower voltages
• 74HC series: CMOS logic with TTL-compatible inputs and supply

For new construction, 74HC CMOS is strongly preferred: lower power, wider supply range, easier to drive.

Fan-out: how many inputs one output can drive. TTL outputs can drive 10 TTL inputs. CMOS outputs can drive hundreds of CMOS inputs (limited by capacitance, not current). Never exceed fan-out limits: outputs driving too many loads show degraded output voltages and incorrect logic behavior.

Gate Propagation Delay

Propagation delay (tpd) is the time from input change to output change. For 74HC series: 5–10 ns. For LS-TTL: 10–20 ns. For relay gates: 1–10 ms.

Delay matters when multiple gates are cascaded: the total delay through a path is the sum of individual gate delays. A logic path with 10 gates at 10 ns each has 100 ns total delay — limiting maximum clock frequency to ~10 MHz (period = 100 ns with margin).

Glitches: when multiple inputs to a gate change simultaneously but at slightly different times, the output may briefly show incorrect values before settling. These transient glitches can propagate through logic and corrupt sequential circuit state. At low clock speeds, glitches decay before the next clock edge; at high speeds, hazard analysis is required.

Static Hazards and Propagation

A static hazard is a momentary output glitch during input transitions where the output should remain constant. Example: a two-level AND-OR circuit with A AND NOT A terms in adjacent product terms — during the transition of A, both terms may momentarily be 0, causing the output to glitch low.

Karnaugh map analysis reveals hazards: if adjacent 1-cells are not covered by a common product term, a static-1 hazard exists between them. Fix by adding a consensus term (extra logic) to cover the transition.

In practice, static hazards only matter for asynchronous circuits (no clock). Clocked synchronous systems sample outputs only at clock edges; if the logic settles before the edge, glitches between clock edges are irrelevant.

Practical Gate Circuit Rules

1. Never leave TTL inputs floating (unconnected) — floating TTL inputs default to logic-1 but are noise-sensitive. Tie unused inputs to Vcc (for NAND) or GND (for NOR) through a 1kΩ resistor.

2. CMOS inputs must never float — floating CMOS inputs can settle at analog voltages between thresholds, causing the input transistors to conduct simultaneously, wasting power and possibly causing damage. Always tie unused CMOS inputs to defined logic levels.

3. Decouple power supplies: place a 100nF ceramic capacitor from Vcc to GND as close as possible to each IC. Switching outputs draw transient currents that create voltage spikes on the power rails; decoupling capacitors absorb these transients locally.

4. Match logic families: TTL output driving CMOS input may have insufficient output voltage. Use 74HCT series (CMOS with TTL input levels) at the boundary between TTL and CMOS systems, or a pull-up resistor on TTL outputs.