Fundamental Gates

Part of Basic Computing

Fundamental logic gates — AND, OR, NOT, NAND, NOR — are the atomic building blocks from which all digital circuits are constructed, each implementable in transistors or relays.

Why This Matters

Every digital system, from a simple timer to the most complex processor, consists ultimately of logic gates. Gates are not abstractions but real circuits: the AND gate in a CPU is a handful of transistors arranged to produce the correct output for every input combination. Understanding gates at this level means understanding the physical foundation of computation.

This matters practically because it enables gate-level circuit design and troubleshooting without dependence on pre-made integrated circuits. While ICs are convenient, an engineer who understands how to build a NAND gate from two transistors can construct computing circuits from first principles if IC supplies are unavailable.

The theory of gates also connects to Boolean algebra: each gate implements a Boolean operation, and the rules of Boolean algebra apply directly to analyzing and designing gate networks.

The NOT Gate (Inverter)

The NOT gate has one input and one output. Output = NOT input: when input is 0, output is 1; when input is 1, output is 0.

Transistor implementation (NPN, common-emitter):

• Input through 10kΩ base resistor to NPN transistor base
• Collector connected through 1kΩ load resistor to +5V
• Emitter to ground
• Output taken at collector

When input is low (0V): transistor is off (base below threshold ~0.7V); collector pulls up to +5V through resistor → output is high (logic 1). When input is high (5V): transistor saturates (turns fully on); collector pulled down close to 0V → output is low (logic 0).

This is the simplest digital circuit and the prototype for all transistor logic. The output voltage doesn’t reach perfect 0V or 5V due to transistor characteristics (saturation voltage ≈ 0.2V, output high ≈ 4.8V) but is well within logic threshold margins.

The AND Gate

Output = A AND B: output is 1 only when both inputs are 1.

Two-transistor AND gate: connect two NPN transistors in series (emitter of first transistor to collector of second, second transistor emitter to ground). When both inputs are high, both transistors saturate and current flows, pulling output low — this is actually a NAND configuration.

Because direct AND from transistors tends to produce NAND naturally, hardware often uses NAND as the native operation and derives AND by adding an inverter.

Using diodes and resistor (DRL logic, simplest but slower): two diodes, anodes to inputs, cathodes tied together to output, with pull-up resistor from output to +5V. When either input is low, its diode conducts and pulls output low. Only when both inputs are high (neither diode conducts) does the pull-up raise the output high.

This gives AND behavior but with limited fan-out and poor noise margins. DRL logic is educational but impractical for real systems.

The OR Gate

Output = A OR B: output is 1 when either or both inputs are 1.

Diode-resistor OR: two diodes, anodes to inputs, cathodes joined, pull-down resistor from output to ground. When either input goes high, its diode conducts and pulls the output high. Only when both inputs are low does the output stay low.

OR from NAND (De Morgan’s law): A OR B = NOT(NOT A AND NOT B). Implement as: NOT A → NAND gate 1 (input tied together), NOT B → NAND gate 2 (input tied together), then NAND(NOT A, NOT B) = A OR B. Three NAND operations total.

NAND and NOR

NAND = NOT(A AND B). Output is 0 only when both inputs are 1. NOR = NOT(A OR B). Output is 1 only when both inputs are 0.

NAND from two transistors in series with shared collector load (NAND is the natural form of the two-transistor series circuit):

• First transistor: A input
• Second transistor: B input, emitter to ground
• Shared load resistor to +5V
• Output at first transistor’s collector

Both inputs high → both transistors on → output low (NAND = 0, consistent with NAND(1,1)=0). Either input low → transistor chain broken → output pulled high (NAND(0,x)=1).

NOR from two transistors in parallel (either transistor can ground the output):

• Two transistors, separate base inputs (A and B)
• Emitters both to ground
• Collectors both tied to same output node through shared load resistor
• Output high only when both transistors off (both inputs low)

NOR is the natural form of parallel transistor stages. NAND is natural for series.

Buffer and Tri-State Buffer

A buffer has the same logic function as a wire: output equals input. Why is it useful? Because it regenerates signal strength — it can source/sink more current than a weak signal can, allowing it to drive many loads without degradation. Also introduces deliberate signal delay.

Non-inverting buffer from two cascaded inverters: first inverter inverts, second inverts back. Net result: same logic level, restored drive strength.

Tri-state buffer (three-state): has an enable input in addition to data input. When enabled, it acts as a buffer (output = input). When disabled, the output is in “high-impedance” state — neither driving high nor low, effectively disconnected. This allows multiple tri-state buffers to share a single bus without conflict: only one is enabled at a time, the others float.

Three-state logic is essential for bus architectures. Without tri-state capability, connecting multiple signal sources to a shared wire would cause conflicts (one source trying to drive high while another drives low, burning through the resistors between them).

Practical Gate Selection

For constructing circuits from off-the-shelf ICs:

74HC series (CMOS, fast, low power, 2–5V supply):

• 74HC00: quad 2-input NAND
• 74HC02: quad 2-input NOR
• 74HC04: hex inverter
• 74HC08: quad 2-input AND
• 74HC32: quad 2-input OR
• 74HC86: quad 2-input XOR
• 74HC125: quad tri-state buffer
• 74HC245: 8-bit bi-directional bus transceiver (tri-state)

NAND and NOR are available in 3-input (74HC10, 74HC27) and 4-input (74HC20, 74HC25) versions for more compact designs.

For a comprehensive gate kit, stock: HC00 (NAND), HC02 (NOR), HC04 (inverter), HC86 (XOR), HC245 (tri-state bus). These five types cover virtually any combinational circuit.