Resistor-Transistor Logic is the easiest logic family to build from discrete parts because its natural gate is a NOR: one base resistor and one transistor per input, all sharing a collector pull-up, so the output goes low if any input is high. NAND is awkward because stacking transistors in series adds a saturation drop per input and eats the thin noise margin, so AND is built as a NOR with inverted inputs and OR as a NOR followed by an inverter. RTL has a fan-out of only about 3 to 5, and two cross-coupled NOR gates make a 1-bit SR latch.
Part of Boolean Logic and Gates
Resistor-Transistor Logic — the earliest transistor logic family, buildable from the simplest possible components with minimal fabrication requirements.
Why RTL Is the First Logic You Can Build
RTL (Resistor-Transistor Logic) was the first widely used transistor-based logic family, used in the early 1960s and in some of the first computers to use transistors rather than vacuum tubes. The Minuteman missile guidance computer used RTL ICs. The earliest Apollo Guidance Computer prototypes used RTL.
For a civilization rebuilding computing from scratch, RTL is important for a different reason: it is the easiest logic family to build from discrete components. The basic NOR gate requires just one resistor and one transistor per input. With a small transistor fabrication capability, RTL is the first working digital logic you can produce.
RTL has real limitations — low fan-out, poor noise margins, slow speed — but it is functional, understandable, and requires the least component variety of any logic family. Building a working RTL circuit is the simplest path from “understanding gates abstractly” to “running digital logic on a bench.”
The RTL NOR Gate
The fundamental RTL gate is the NOR gate. For a 2-input RTL NOR:
Components:
- Resistors Rb1 and Rb2 (typically 450–680 Ω) from inputs A and B to transistor bases
- Transistors Q1 and Q2 (NPN, 2N2222 or equivalent), emitters to GND, collectors to common output node
- Pull-up resistor Rc (typically 640 Ω) from VCC (+3.6V for original RTL or +5V for modernized) to the common collector node
If either input A or B is HIGH (≥2.0V), the corresponding transistor saturates, pulling the output node to near GND. Only if both inputs are LOW (<0.8V) do both transistors stay off, and Rc pulls the output HIGH.
This is NOR: output HIGH only when all inputs are LOW.
For an N-input NOR, add N transistors in parallel sharing the same collector node, each with its own base resistor from the respective input.
The RTL Inverter
An inverter is a 1-input NOR: a single transistor with one base resistor and one pull-up.
Input HIGH → transistor on → output LOW. Input LOW → transistor off → output HIGH (pulled up by Rc).
This is identical to the transistor inverter described in the NOT gate article, with the specific resistor values characteristic of RTL. RTL standardizes on particular resistor values that balance speed, power dissipation, and fan-out within the family.
The RTL NAND Gate
NAND is not a natural RTL gate. NOR gets extra inputs almost for free, by adding transistors in parallel, each with its own base resistor, all sharing one collector pull-up. NAND requires the opposite topology: transistors stacked in series, emitter-to-collector, so the output only pulls LOW when every stacked transistor is saturated at once.
For a 2-input RTL NAND:
Components:
- Resistors Rb1 and Rb2 from inputs A and B to the transistor bases (same values as the NOR gate)
- Transistors Q1 and Q2 (NPN), stacked: Q1 collector at the output node, Q1 emitter wired to Q2 collector, Q2 emitter to GND
- Pull-up resistor Rc from VCC to the output node (same as the NOR gate)
If either input is LOW, its transistor is off, breaking the series path to GND, and Rc pulls the output HIGH. Only when both A and B are HIGH do both transistors saturate, completing the path and pulling the output LOW.
This is NAND: output LOW only when all inputs are HIGH.
Why it’s awkward: each transistor in the stack adds its own saturation voltage drop (Vce(sat)) in series with the others. A parallel NOR only ever has one transistor’s drop between the output node and GND, no matter how many inputs it has. A series NAND stacks a drop per input. RTL’s noise margins are already thin — this page’s own figures are NMH ≈ 0.5V and NML ≈ 0.6V — and every added stacked transistor eats directly into that margin. In practice this puts a hard ceiling on RTL NAND at 2 inputs; a 3-input stack is unworkable.
This is the real reason NOR, not NAND, is the gate RTL is built around: adding a NOR input means one more independent transistor to ground sharing the collector node, costing almost nothing in noise margin. Adding a NAND input stacks another saturated drop in series, directly consuming margin that RTL can’t spare. Parallel scales for free; series doesn’t. NOR is also a universal gate on its own — AND, OR, and the inverter all build from it (see below) — so a single characterized, tested NOR circuit is enough to build an entire machine from. The Block II Apollo Guidance Computer took this to its conclusion: its logic section used roughly 4,100 identical dual 3-input NOR gate ICs as effectively the only logic IC type in the machine, with every register, adder, and flip-flop built by wiring the same NOR gates differently. (The one exception was a sense amplifier in the core-memory read path.)
Consistent with this, no commercial RTL family appears to have shipped a native RTL NAND IC. Fairchild’s µL900 series and Motorola’s MRTL catalog are built from n-input NOR gates, inverters/buffers, and flip-flops — no NAND part. When designers needed NAND, they reached past RTL entirely for DTL’s diode-AND input structure, which is also the easier circuit to hand-build from scrounged diodes if you need true NAND at the bench.
The RTL AND Gate
Build this as a NOR with inverted inputs, not as a NAND followed by an inverter. By De Morgan’s law, NOR(Ā, B̄) = A·B directly.
Components:
- An RTL inverter on input A, and a second RTL inverter on input B (as built above)
- A standard 2-input RTL NOR gate, fed by the two inverter outputs
Invert A and invert B, then feed both inverted signals into the 2-input NOR. No output inverter is needed — the NOR’s own output is already A AND B.
Why this way: a NAND-plus-inverter approach would mean first building the fragile series-stack NAND topology above just to immediately undo it with an inverter — paying for a second circuit with its own saturation and noise-margin budget to get a gate you then throw away. The De Morgan route only ever uses the NOR and inverter cells already built and characterized earlier on this page. This is also the approach the Apollo Guidance Computer used.
The RTL OR Gate
The easiest of the three: a standard 2-input NOR followed by an inverter.
Components:
- A standard 2-input RTL NOR gate, fed directly by inputs A and B
- An RTL inverter on the NOR’s output
No input inversion, no series stacking — just one extra gate stage on the output of a NOR you’ve already built.
Logic Levels and Supply Voltage
Original RTL (e.g., Fairchild µL900 series) used +3.6V supply:
- Logic 1: 2.0–3.6V (typically 3.1V loaded)
- Logic 0: 0–0.2V (transistor saturation ≈ 0.1V)
- VIH = 1.5V, VIL = 0.8V
- NMH ≈ 0.5V, NML ≈ 0.6V
Noise margins are modest — RTL is not suitable for very noisy environments.
For discrete construction using +5V:
- Increase Rc to 1.5 kΩ to maintain similar logic levels proportionally
- Increase Rb to 1.0 kΩ
- NPN transistors with low Vce_sat and hFE > 40 work well
The small supply voltage of 3.6V is not mandatory for discrete RTL. Using +5V with proportionally scaled resistors gives better compatibility with modern ICs.
Fan-Out Limitations
RTL has low fan-out, typically 3 to 5 in the original family. The limitation comes from current: when the driving gate output is HIGH, Rc must supply current to all driven gate base resistors. Each RTL input draws approximately VCC/Rb = 5V/640Ω ≈ 8 mA from the preceding gate’s pull-up resistor. The output voltage HIGH level falls as more loads are connected.
With 5 loads drawing 8 mA each = 40 mA through Rc = 640 Ω: voltage drop = 40 mA × 640 Ω = 25.6 V — clearly impossible in a 5V system. This calculation shows why original RTL operated at low voltages with higher base resistors.
For practical 5V discrete RTL with Rb = 5 kΩ: each load draws 1 mA, 5 loads draw 5 mA through Rc = 2.2 kΩ: voltage drop = 11V. Still too much for 5 loads at full current. Fan-out of 3–4 is more realistic.
To increase fan-out, add an emitter follower buffer: a transistor with emitter as output and no Rc. The emitter follower provides current gain without voltage inversion. Place a buffer at any node driving more loads than the standard fan-out allows.
Building an SR Latch from Two NOR Gates
A 1-bit SR latch from two RTL NOR gates:
Gate 1 (Q output): NOR(R, Q_bar) → Q Gate 2 (Q_bar output): NOR(S, Q) → Q_bar
Wire the output of Gate 1 to one input of Gate 2, and the output of Gate 2 to one input of Gate 1 (feedback). Connect switches to the free inputs (S and R). Add LED indicators on both Q and Q_bar.
Total components: 4 transistors, 4 base resistors (Rb), 2 pull-up resistors (Rc), 2 switches, 2 LEDs, 2 current-limiting resistors.
Test:
- Set S=1, R=0: Q should latch HIGH (LED on), Q_bar LOW
- Release S (both inputs LOW): Q stays HIGH (latch holds state)
- Set R=1, S=0: Q should reset to LOW, Q_bar HIGH
- Release R: Q stays LOW (latch holds state)
This is a working 1-bit memory cell — the first experience of a circuit that remembers its last state.
RTL vs. DTL
RTL progresses naturally to DTL:
- RTL: input resistors directly drive transistor bases
- DTL: diodes at inputs provide isolation and better noise margins
The evolution from RTL to DTL improved noise margins from ~0.5V to ~1.0V and increased fan-out. DTL then evolved to TTL (replacing input diodes with multi-emitter transistors) for still faster switching.
RTL is the starting point. Its simplicity makes it the right first step for anyone building digital logic from scratch, even if the goal is eventually to graduate to DTL or TTL.