Silicon wafers are cut from a bar 0.3 to 0.5 mm thick with a thin steel wire carrying silicon carbide grit, or with a thin grinding wheel, then polished on one face with progressively finer abrasive. The arithmetic is unforgiving: a wafer cut from a 3 cm bar yields about 0.03 W in full sun at 4% efficiency, so a 100 W array would need several thousand wafers and about 2 metres of refined bar.

Slicing a purified silicon ingot into wafers for cells, and what the wafer count means for a village array.

Thin Wafers Save Silicon But Break Easily

The carrier says to slice the p-type ingot into wafers 0.3–0.5 mm thick using either a thin abrasive wire saw (steel wire with silicon carbide grit) or a thin grinding wheel, and to polish one face with progressively finer abrasive. Thinner wastes less silicon but is more fragile. The silicon is the product of everything upstream (Quartz Reduction, Zone Refining), so every wafer broken in cutting is hard to replace. The zone-refining step in the carrier makes a bar 30–50 cm long and 3 cm in diameter.

Fabrication Basics gives wafer preparation for germanium: lap and etch a 0.5–1.0 mm wafer and use it within one to two hours of etching, and it expects only 40–60% functional devices in early batches. The same expectation of losses fits a first silicon run.

What You Need

  • A purified, doped silicon bar — Doping with Phosphorus and Boron
  • Steel wire and silicon carbide grit, or a thin grinding wheel, with a lubricant such as water
  • A rigid frame to hold the bar and guide the wire
  • A soft, padded work surface (carrier)
  • Fine abrasives for polishing
  • Eye protection and a respirator

Method: Slice And Polish

Step 1: Mount the bar rigidly so it cannot rock; any wobble cracks the wafer.

Step 2: Run the wire with grit and lubricant, letting the abrasive do the cutting under light load. Forcing the wire breaks the wafer.

Step 3: Remove each wafer onto a soft pad; handle by the edges.

Step 4: Polish one face with progressively finer abrasive, as the carrier says.

Step 5: Inspect for cracks by holding to the light; reject cracked wafers.

Worked Example: How Many Wafers, How Much Power

Take the carrier’s bar of 3 cm diameter. The wafer area is π × 1.5² = 7.07 cm². In full sun the corpus gives about 1,000 W/m², which is 0.1 W/cm² (Solar Energy Fundamentals). The incident power on one wafer is 7.07 × 0.1 = 0.707 W; at the carrier’s mid-range 4% efficiency the output is 0.707 × 0.04 = 0.028 W, about 0.03 W, and across the carrier’s 2–8% range 0.014 to 0.057 W.

A 100 W array then needs 100 ÷ 0.0283 = 3,534 wafers at 4%. Count the wafers per bar: with 0.4 mm wafers (mid-range) and an assumed 0.2 mm lost to the wire kerf, each wafer uses 0.6 mm of bar, so a 30 cm bar (the short end of the carrier’s 30–50 cm) gives 300 ÷ 0.6 = 500 wafers. Then 3,534 ÷ 500 = 7.1 bars of 30 cm, more than 2 metres of refined silicon. The kerf figure is assumed.

The current confirms the scale: at 4% and 0.5 V per cell (carrier), the current density is 0.1 × 0.04 ÷ 0.5 = 0.008 A/cm², so a 7.07 cm² wafer gives 0.057 A. The carrier’s panel table assumes cell current around 0.5 A, which at this density needs a cell of 0.5 ÷ 0.008 = 62.5 cm², about 8 cm square, not a slice of a 3 cm bar.

Common Mistakes

  • Cutting thick to save wafers — each wafer wastes silicon and cell current is no higher
  • Forcing the wire — breaks the wafer and the wire
  • Dry cutting — grit and heat crack the silicon and raise dust
  • Planning a panel without counting wafers — the totals above are the plan

Safety

Silicon dust, grit and a cutting wire

Cutting and polishing make fine silicon and silicon carbide dust that is inhaled; cut wet, keep the slurry in a tray, and wear a respirator (Dust & Respiratory Protection). A moving wire under tension can whip if it breaks, and wafer edges are razor sharp, so wear eye protection and gloves and do not clear wafers with bare hands.

What’s Next