SR Latch
Part of Boolean Logic and Gates
The simplest bistable circuit — two cross-coupled gates that hold one bit of state, forming the foundation for all flip-flops and memory cells.
Why This Matters
The SR latch is the most fundamental memory element in digital electronics. Two gates wired in a feedback loop can hold one of two stable states indefinitely without a power-off. It remembers its last commanded state and holds it until explicitly changed. This bistability is the physical basis for all digital memory — from the simplest switch debouncer to SRAM cells in modern computers.
Every edge-triggered flip-flop is built from latches internally. Every flip-flop contains at least two SR latches (master-slave configuration) at its core. Understanding the SR latch means understanding the atom of digital memory.
The SR latch also appears constantly in practical circuits: debouncing mechanical switches, implementing set-reset control logic for motors and indicators, and as the output stage of many sensor interface circuits.
The NOR-Based SR Latch (Active-High)
The NOR SR latch uses two cross-coupled NOR gates:
- Gate 1: Q = NOR(R, Q_bar)
- Gate 2: Q_bar = NOR(S, Q)
Where Q and Q_bar are the two complementary outputs, and each gate’s output feeds into the input of the other.
Truth table (active-high inputs):
| S | R | Q_next | Q_bar_next | Notes |
|---|---|---|---|---|
| 0 | 0 | Q | Q_bar | Hold state |
| 0 | 1 | 0 | 1 | Reset |
| 1 | 0 | 1 | 0 | Set |
| 1 | 1 | 0 | 0 | Forbidden |
The SR=11 state is forbidden because it drives both Q and Q_bar to 0 simultaneously, violating the requirement that they be complements. When both S and R subsequently return to 0 from the 11 state, the latch settles to an unpredictable state determined by which gate wins the race.
The NAND-Based SR Latch (Active-Low)
The NAND SR latch uses two cross-coupled NAND gates:
- Gate 1: Q = NAND(S_bar, Q_bar)
- Gate 2: Q_bar = NAND(R_bar, Q)
Truth table (active-low inputs — assert LOW to activate):
| S_bar | R_bar | Q_next | Notes |
|---|---|---|---|
| 1 | 1 | Q | Hold state |
| 1 | 0 | 0 | Reset (R asserted) |
| 0 | 1 | 1 | Set (S asserted) |
| 0 | 0 | 1 | Forbidden (both outputs forced HIGH) |
The forbidden state for NAND is S_bar=R_bar=0 (both inputs active-low, so both asserted). This forces both Q and Q_bar to 1 simultaneously — again violating complementarity.
Active-low inputs are natural for NAND latches. When building push-button set/reset circuits, the buttons pull the input to GND (active low) through the NAND input, matching this convention.
Bistable Operation and Feedback
The key to understanding the latch is the feedback path. With S=R=0 (NOR latch), both inputs are inactive. Consider the current state Q=1, Q_bar=0:
- Gate 1 input: R=0, Q_bar=0 → Q = NOR(0,0) = 1 ✓ (self-consistent)
- Gate 2 input: S=0, Q=1 → Q_bar = NOR(0,1) = 0 ✓ (self-consistent)
The circuit satisfies its own equations — Q=1 is a stable state. Similarly, Q=0, Q_bar=1 is the other stable state. The latch will remain in whichever state it was last set to, indefinitely (as long as power is maintained).
This is bistability: two stable operating points. The latch can be disturbed from one stable state to the other only by applying S or R pulses. External noise smaller than the noise margin cannot inadvertently switch the state — the feedback regenerates the state against small perturbations.
Building and Testing a NAND SR Latch
Parts: one 74LS00 (quad NAND IC), two push buttons, pull-up resistors (10 kΩ), two LEDs with 330 Ω resistors, +5V supply.
Wiring:
- Wire NAND gate 1: inputs are S_bar (from button 1, normally HIGH through pull-up) and Q_bar (from output of gate 2).
- Wire NAND gate 2: inputs are R_bar (from button 2, normally HIGH) and Q (from output of gate 1).
- Connect Q output to a green LED (through 330 Ω to GND).
- Connect Q_bar output to a red LED (through 330 Ω to GND).
Testing:
- Initially (no buttons pressed, S_bar=R_bar=1): latch holds previous state. One LED on, the other off.
- Press button S (S_bar goes LOW): Q → 1, Q_bar → 0. Green LED on, red off. Release button: state holds.
- Press button R (R_bar goes LOW): Q → 0, Q_bar → 1. Red LED on, green off. Release button: state holds.
This is the simplest demonstration that digital circuits can have memory without a clock.
Switch Debouncing with SR Latch
Mechanical switches bounce — when pressed, the contacts make and break several times in milliseconds before settling. This produces multiple transitions on the input signal, which digital circuits interpret as multiple button presses.
An SR latch deounces a switch wired with two contacts (SPDT — single pole, double throw):
- When switch moves to position A: S is momentarily grounded (asserted)
- First contact sets the latch Q=1
- Bouncing of contact A may briefly unassert S, but Q remains 1 (latch holds)
- The latch output is clean — one edge, regardless of bounce
Single-contact (SPST) switches require a different debounce approach (RC network with Schmitt trigger), but SPDT switches connected to an SR latch are the cleanest and most reliable solution.
SR Latch as Foundation for Flip-Flops
The D flip-flop (edge-triggered) is internally a master-slave SR latch pair:
- Master latch: transparent during CLK=0, holds state during CLK=1
- Slave latch: transparent during CLK=1 (transfers master output to Q), holds during CLK=0
The master-slave arrangement ensures that the output changes only at the clock edge, achieving edge-triggering from level-sensitive latches. All practical flip-flop designs build on this principle.