Register

Part of Boolean Logic and Gates

A group of flip-flops storing a multi-bit value — the fundamental storage unit inside every CPU, holding operands, addresses, and intermediate results.

Why This Matters

A register is the most basic memory structure in a processor. It stores one word of data — typically 8, 16, 32, or 64 bits — in a bank of flip-flops that share a clock signal. When a CPU performs an addition, both operands come from registers, the result goes to a register, and the program counter (which tracks where in code the CPU is executing) is itself a register.

Understanding registers bridges the gap between individual flip-flops and the working memory of a CPU. Building a simple register bank from discrete flip-flops demonstrates concretely how data is held and manipulated at the hardware level. It is also the most immediately useful circuit for connecting sensing, counting, or computation results to an output display.

What a Register Is

An N-bit register is simply N D flip-flops sharing a common clock input. Each flip-flop stores one bit. All flip-flops receive the same clock edge simultaneously, so the entire N-bit word is captured and held in one clock cycle.

An 8-bit register has:

• 8 D inputs (D0–D7)
• 1 clock input (CLK) shared by all flip-flops
• 8 Q outputs (Q0–Q7)
• Optionally: a common asynchronous clear (CLR) and/or preset (PRE)

Loading a value: set the D inputs to the desired 8-bit pattern, then pulse the clock. The 8-bit value is stored and held on Q.

Reading: the Q outputs continuously show the stored value. They can drive downstream logic at any time without destroying the stored content.

Types of Registers

Parallel-in parallel-out (PIPO): data is loaded and read on all bits simultaneously. This is the standard register for holding operands in arithmetic or data bus connections.

Serial-in serial-out (SISO): data enters and exits one bit at a time, shifting through the chain of flip-flops on each clock edge. This is a shift register used for delay lines or serial communication.

Serial-in parallel-out (SIPO): data enters serially one bit per clock, and after N clocks all N bits are available in parallel. This is the serial-to-parallel converter used in UARTs and SPI receivers.

Parallel-in serial-out (PISO): all N bits are loaded simultaneously, then shifted out one bit per clock. This is the parallel-to-serial converter used in UART transmitters and SPI senders.

Building an 8-Bit Parallel Register

Using eight D flip-flops:

1. Connect all CLK inputs to a shared clock line.
2. Connect all CLR inputs (if active-low) to a shared reset line (tie HIGH through 10 kΩ if no reset is needed).
3. D0–D7 are the independent data inputs.
4. Q0–Q7 are the outputs.

For a practical data register that can be loaded from a bus:

• Add 8 AND gates, one per bit: Data_in_n AND Load_enable
• Connect each AND output to the corresponding D input
• When Load_enable = 0, all D inputs are forced to 0 and the flip-flops reset on clock edges
• When Load_enable = 1, data flows to the D inputs and is loaded on the next clock edge

Alternative: use D flip-flops with a mux on each D input:

• D input = MUX(Q, Data_in, Load_enable)
• When Load_enable = 0, D = Q (feedback, register holds current value)
• When Load_enable = 1, D = Data_in (register loads new value)

This enables selective loading: the register only updates when Load_enable is asserted.

Shift Register Operation

A shift register is a chain of flip-flops where the Q of each stage connects to the D of the next:

• Q0 → D1 → Q1 → D2 → Q2 → … → QN-1

On each clock edge, the data in each stage moves to the next stage. New data enters at D0 (the serial input), and data exits from QN-1 (the serial output).

An 8-bit shift register takes 8 clock pulses to fully load 8 bits of serial data. After 8 clocks, the parallel outputs Q0–Q7 hold the 8 bits that were clocked in, available for parallel reading. This is SIPO operation.

For PISO operation: add a parallel load function (either a mux or asynchronous preset/clear on each stage). Asserting the load signal simultaneously stores all parallel input bits into all flip-flops. Then shift out serially.

Universal Shift Register

A universal shift register can perform all four register modes (SIPO, PISO, SISO, PIPO) under control of two mode select bits. Each stage’s D input is driven by a 4-to-1 mux selecting among:

• Hold (Q feedback — no change)
• Shift right (left neighbor’s Q)
• Shift left (right neighbor’s Q)
• Parallel load (external data input)

The 74LS194 is a classic TTL 4-bit universal shift register IC. Cascading two gives 8 bits.

Registers in a CPU

A typical 8-bit CPU has:

• Accumulator (A): the primary working register for arithmetic and logic operations
• General-purpose registers (B, C, D, E, H, L): data holding registers
• Program Counter (PC): 16-bit register holding the address of the next instruction
• Stack Pointer (SP): 16-bit register pointing to the current top of the stack in memory
• Status/Flags register (F): holds condition bits — Zero flag, Carry flag, Sign flag, Overflow flag

All are banks of flip-flops, varying only in their width and the control logic surrounding them. The flags register is written by arithmetic/logic operations and read by conditional branch instructions — it is the mechanism by which the CPU makes decisions based on computed results.