Quality Sorting

Part of Semiconductors

Measuring, binning, and selecting semiconductor devices by performance parameters for reliable circuit use.

Why This Matters

Primitive semiconductor fabrication produces devices with wide parameter variation. Even a well-controlled alloy junction process yields transistors with current gain (hFE) ranging from 30 to 300. A circuit designed for hFE=100 may fail with a device at either extreme. Without sorting, you cannot predict circuit performance from design calculations.

Quality sorting transforms a batch of variable devices into graded lots with known specifications. Each device is measured, its parameters recorded, and it is placed in a bin covering a specific parameter range. When designing a circuit, you select devices from the appropriate bin. Variation within a bin is small; the circuit works as designed.

This practice is not a concession to poor fabrication — even modern precision transistors are sorted and binned. The difference is that modern bins are tight (hFE 200-300 in one bin, 300-450 in another) while primitive fabrication bins are wide (50-100, 100-200). As fabrication improves, bin definitions tighten and design constraints loosen.

Beyond enabling reliable circuits, systematic quality data reveals fabrication process problems: excessive low-gain outliers indicate base thickness non-uniformity or contamination; high-leakage clusters indicate a bad material lot; bimodal gain distribution indicates two distinct formation processes in one batch.

Parameters to Measure

For diodes, measure for each device:

1. Forward voltage (V_F) at 1 mA: Distinguishes silicon from germanium; indicates junction quality. Sort into 50 mV bins (e.g., 0.55-0.60V, 0.60-0.65V, 0.65-0.70V for silicon).
2. Reverse leakage (I_R) at rated voltage: Quality and purity indicator. Sort: < 1 µA (A grade), 1-10 µA (B grade), 10-100 µA (C grade), > 100 µA (reject).
3. Breakdown voltage (V_BR): Maximum usable reverse voltage. Sort by 10V intervals for designs requiring specific ratings.

For transistors (BJT), measure:

1. DC current gain (hFE or β): Most important parameter. Measure at a representative collector current (e.g., 1 mA for signal transistors, 100 mA for power transistors). Sort into gain bins: 20-40, 40-80, 80-160, 160-320 (approximately doubling ranges).
2. Collector-emitter leakage (ICEO): Leakage with base open. Good transistor: < 1 µA (silicon), < 10 µA (germanium).
3. Base-emitter voltage (VBE) at 1 mA: Forward junction voltage. Sort within 50 mV for matched circuit use.
4. Collector-emitter saturation voltage (VCEsat): Voltage when fully on. Should be < 0.3V for silicon at rated current.
5. Breakdown voltage (BVCEO): Maximum collector voltage with base open.

For complete characterization, also measure transition frequency (fT) — the frequency where current gain drops to 1. This requires an RF bridge or network analyzer and is aspirational for early fabrication. Prioritize DC parameters first.

Measurement Setup and Procedure

Basic transistor test jig:

• Variable base current source: 5V supply through a rotary-switched resistor bank (1M, 470k, 220k, 100k, 47k, 22k, 10k Ω) providing base currents from ~5 µA to ~0.5 mA.
• Collector circuit: 9V supply through a 100Ω resistor in series with milliammeter (or voltmeter across the resistor).
• Emitter: ground.
• Socket accepting transistors in standard pinout (mark E, B, C clearly).

Measurement sequence (5-10 seconds per device):

1. Insert transistor. Set base resistor to give IB = 10 µA.
2. Record VCE (measure across transistor) and IC (read current meter).
3. hFE = IC / IB. Record.
4. Switch base resistor to open (no base current). Measure ICEO (collector leakage).
5. Remove transistor. Record on paper ledger: device ID, hFE, ICEO, and any anomaly notes.

Paper recording system: Pre-printed tally sheet with device number column, parameter columns, and bin column. Fill in as you measure. Transfer bin assignments to the device itself (mark with colored marker on the package or body) and to a card that goes into the storage bin.

Batch statistics: After measuring all devices in a batch, calculate mean and standard deviation for each parameter. Compare to previous batches. Widening distribution indicates process degradation. Shifts in mean indicate systematic process change (temperature drift in furnace, new dopant lot, different semiconductor crystal).

Binning System and Physical Organization

Physical bins: Small labeled containers — paper envelopes, labeled compartments in a wooden box, or small glass vials. Label clearly: device type, parameter measured, value range, date fabricated.

Example bin label: “Ge PNP Alloy — hFE 80-160 — VCE 20V max — Jan 2027 Batch #12”

Color coding: A simple color code accelerates selection. For hFE bins: green = 80-160 (standard), blue = 160-320 (high gain), yellow = 40-80 (low gain), red = reject or untested.

Inventory tracking: Ledger book recording: bin ID, device type, quantity, date fabricated, batch number, key parameter stats. Update each time devices are withdrawn. Never run a bin below reserve stock (5 devices) before fabricating replacements.

Storage conditions: Germanium devices are more temperature-sensitive than silicon. Store in a cool location (below 25°C). Avoid humidity — moisture can penetrate imperfect packages and cause leakage current increases. Silica gel desiccant in storage containers extends shelf life.

Matching for Critical Applications

Some circuits require matched devices — pairs or quads with identical or closely matched parameters:

Differential amplifier: Both transistors must have matched VBE (within 5 mV) and hFE (within 10%). Mismatch causes DC offset that varies with temperature. Sort measured devices into matched pairs: record VBE to nearest 1 mV, group pairs within 5 mV window.

Push-pull output stage: The NPN and PNP transistors should have similar hFE for symmetric current handling. Also match saturation voltages.

Current mirror: Two transistors with identical VBE carry equal currents. Match to within 2 mV for 2% current accuracy, 10 mV for 10% accuracy.

Matching procedure: Measure all candidates at identical conditions (same VCE, same IC, same temperature). Record VBE and hFE. Sort by VBE in ascending order. Pair adjacent devices (1st with 2nd, 3rd with 4th, etc.) — adjacent ranked devices have minimum spread. Reject any pair where spread exceeds specification.

Thermal matching: In critical circuits (low-drift instrumentation amplifiers), matched devices should be thermally coupled — mounted on the same heatsink or in the same package. Temperature gradients across a circuit board cause matched electrical parameters to unmatch as different devices reach different temperatures.

Using Quality Data for Process Improvement

Each batch’s quality data is an input to improving fabrication:

Low average hFE: Base too wide (alloy penetration too shallow or uneven), or minority carrier lifetime too short (purification inadequate). Try longer/hotter alloy cycle, or improve germanium purity.

High hFE spread (wide distribution): Alloy dot size inconsistent. Improve consistency of indium dot preparation — weigh to nearest 0.1 mg, cut from sheet rather than tearing.

High leakage in many devices: Contamination in batch. Trace to specific process step: Was the reducing atmosphere adequate? Was the germanium wafer from a bad ingot section? Was the indium from a new lot?

Systematic shift batch-to-batch: A furnace temperature drift, a new dopant lot, a change in operator technique. Compare batch logs for the variable. Control the process variable more tightly.

Quality sorting is the feedback mechanism that makes semiconductor manufacturing self-improving. Without it, each batch is independent with no learning. With it, each batch teaches the next one how to be better.