OR Gate

5 min read

Parent
🔲
Basic Logic Gates
NOT, AND, OR in transistors
Current
🔀
OR Gate
Output high when any input is high

OR Gate

Part of Boolean Logic and Gates

A fundamental logic gate that outputs 1 when any input is 1 — used for flag aggregation, alarm systems, and bus conflict detection.

Why This Matters

The OR gate is one of the three primitive Boolean operations, alongside AND and NOT. It implements logical disjunction: the output is true if at least one condition is true. This is the natural circuit for alarm aggregation, interrupt consolidation, and any scenario where multiple independent signals can trigger the same response.

OR gates appear throughout digital systems: a CPU’s interrupt controller ORs multiple peripheral interrupt lines together. An error detection circuit ORs individual error flags. A display brightness circuit ORs the blanking signals from horizontal and vertical sync circuits.

Understanding how OR is physically implemented — and why direct CMOS OR is synthesized as NAND(NOT-A, NOT-B) rather than a direct construction — builds intuition for the relationship between logic families and circuit implementation.

Truth Table

ABA OR B
000
011
101
111

Boolean notation: Y = A + B (the plus sign denotes OR in Boolean algebra, not addition).

OR is the inclusive or — the output is 1 even when both inputs are 1. This distinguishes it from XOR (exclusive or), where both-inputs-high produces 0.

Diode OR Gate

The simplest physical OR gate uses diodes. For a 2-input diode OR:

  • Anode of D1 connected to input A
  • Anode of D2 connected to input B
  • Cathodes of D1 and D2 joined at output node
  • Pull-down resistor from output to GND (to pull the output low when both inputs are low)

When A or B (or both) is HIGH, the corresponding diode forward-biases and the output rises to Vin - 0.6V (one diode drop below input). When both inputs are LOW, both diodes are reverse-biased and the pull-down holds the output at GND.

Limitation: the output voltage is one diode drop (≈0.6V) below the input. For multi-level cascaded diode logic, these voltage drops accumulate and eventually degrade logic levels to unusable values. For a single OR stage followed by a transistor amplifier stage, this is acceptable. Diode logic is the first half of DTL.

OR from Transistors (RTL/DTL)

In resistor-transistor logic, OR is implemented with transistors in parallel, with the output taken from before the final common-emitter stage — but pure OR without inversion would require an extra inverter stage, making NAND (OR followed by NOT, then NOT again) more natural.

A more practical approach for RTL OR:

  • Two transistors Q1 and Q2 in parallel (emitters to GND, collectors to common node)
  • Pull-up resistor from VCC to the common collector node
  • This produces NOR (output is LOW when either input is HIGH)
  • Add a transistor inverter after to get OR

Since OR requires more transistors than NOR, digital designers typically work with NOR and NAND primitives, using DeMorgan’s theorem to recast OR where needed.

OR from NAND Gates (DeMorgan)

By DeMorgan’s theorem: A OR B = NOT(NOT-A AND NOT-B) = NAND(NOT-A, NOT-B)

Implementation with three NAND gates:

  1. Gate 1: NOT-A = NAND(A, A)
  2. Gate 2: NOT-B = NAND(B, B)
  3. Gate 3: Y = NAND(NOT-A, NOT-B) = A OR B

This is the standard NAND-only OR implementation. Three NAND gates replace one OR gate.

Alternatively, using a NOR gate as the natural complement: OR(A,B) = NOT(NOR(A,B)), requiring one NOR gate and one inverter (or another NOR as inverter) — two gates for OR from NOR.

OR in CMOS

CMOS does not implement OR directly. Instead, it implements NOR naturally (PMOS in series, NMOS in parallel) and then adds a CMOS inverter. The resulting circuit (NOR + NOT) equals OR. Most CMOS OR gate cells in standard cell libraries are internally NOR-NOT.

The 74HC32 is a quad 2-input OR gate in CMOS. Internally, each gate is NOR followed by NOT, but externally the pin behavior is simply OR.

Multi-Input OR

An 8-input OR gate can be built as a tree of 2-input OR gates:

  • First level: four 2-input OR gates on pairs of inputs (OR01, OR23, OR45, OR67)
  • Second level: two 2-input OR gates (OR(OR01, OR23), OR(OR45, OR67))
  • Third level: one 2-input OR gate combining the two second-level results

Total: seven 2-input OR gates. Balanced tree minimizes propagation delay.

Alternatively, a single 8-input OR with a direct sum-of-inputs implementation using a wired-OR (diode tree) followed by a transistor stage.

OR Applications

Interrupt consolidation: a microprocessor has one interrupt pin but multiple peripherals. OR the interrupt lines from all peripherals into the single INT input. When any peripheral requests service, the processor is interrupted.

Error flag aggregation: multiple error detect circuits each set an error flag. OR all flags into a single system-error output that triggers an alarm or halt.

Bit-field OR masking: to set specific bits in a register, OR it with a mask. register |= 0b00001100 sets bits 2 and 3 without affecting other bits. This is OR used as a bitwise set operation in software.

Wired-OR: in some logic families (open-collector TTL, open-drain CMOS), multiple output pins can be connected together. The combined output is LOW if any output is driven LOW — this is a negative-logic AND (positive-logic OR). Pull to VCC with a single resistor and all gates pulling low give OR behavior without additional logic gates. Used in I2C bus arbitration.