NOT Gate (Inverter)
Part of Boolean Logic and Gates
The simplest active logic element — a single-transistor circuit that inverts a logic signal, generating the complement needed by nearly every digital circuit.
Why This Matters
The NOT gate (inverter) is the most basic active logic element. It has one input, one output, and one operation: invert. When input is 0, output is 1. When input is 1, output is 0.
Despite its simplicity, the inverter is indispensable. Every latch and flip-flop needs complementary signals. NAND and NOR implementations require inversions. DeMorgan transformations introduce inversions. Counters, decoders, and shift registers all depend on inverters at key points.
More importantly, the inverter is the simplest circuit that demonstrates transistor gain enabling logical computation. Building your first working inverter — a single transistor, two resistors, and a power supply — is the foundational step from which all digital electronics follows.
Truth Table
| A | NOT A |
|---|---|
| 0 | 1 |
| 1 | 0 |
Boolean notation: Y = NOT A = Ā = A’ = ¬A
The schematic symbol is a triangle (buffer) with a circle (bubble) on the output. The bubble specifically means inversion — when you see a bubble on any gate pin, that pin’s logical sense is inverted.
Transistor Inverter Circuit
A single NPN transistor in common-emitter configuration implements a NOT gate:
Components:
- NPN transistor (2N2222, BC547, or equivalent)
- Input resistor Rb (typically 10 kΩ) from input to base
- Pull-up resistor Rc (typically 1–4.7 kΩ) from VCC to collector
- Emitter connected directly to GND
- VCC = 5V
Operation when input = HIGH (≈5V):
- Current flows through Rb into base
- Base current saturates transistor (collector-emitter acts like a closed switch)
- Collector pulled to near GND through Rc (Vce_sat ≈ 0.2V)
- Output = LOW ✓
Operation when input = LOW (0V):
- No base current flows
- Transistor cut off (collector-emitter acts like open circuit)
- Collector pulled to VCC through Rc (output ≈ VCC)
- Output = HIGH ✓
Choosing Component Values
The key design choice is ensuring the transistor fully saturates (switches fully on) when input is HIGH.
Required base current: Ib_min = Ic / hFE
Where Ic is the expected load current (determined by what the output drives) and hFE is the transistor’s DC current gain (typically 100–300 for small-signal transistors).
Example: output drives 5 mA load (LED + resistor), transistor hFE = 100. Required Ib_min = 5 mA / 100 = 50 µA.
With Vin = 5V and Vbe = 0.7V: Ib = (Vin - Vbe) / Rb = (5 - 0.7) / Rb
For Ib = 50 µA: Rb = 4.3 / 0.00005 = 86 kΩ.
Use Rb = 47 kΩ for comfortable margin (gives about 90 µA, safely saturating).
For logic gate cascading (not driving high-current loads), Rc = 2.2 kΩ and Rb = 10 kΩ is a standard starting point.
Fan-Out Considerations
The output of an inverter must supply (or sink) current for all downstream gate inputs. Fan-out is limited by:
- Sinking capacity: when output is LOW, the transistor must absorb all current from the driven inputs without Vce_sat rising above VIL_max of the driven gates.
- Sourcing capacity: when output is HIGH, Rc must supply enough current for all driven inputs while keeping output voltage above VOH_min.
For TTL logic driving TTL logic, standard fan-out is 10 (74LS driving 74LS). For discrete transistor gates, calculate explicitly.
If fan-out is exceeded, add an emitter follower buffer between the inverter and the load: a transistor with its emitter as output and no Rc. The emitter follower has high input impedance and can source more current.
CMOS Inverter
In CMOS, an inverter is built from one PMOS and one NMOS transistor in series:
- PMOS source to VCC, NMOS source to GND, gates tied together (input), drains tied together (output).
When input is LOW: PMOS is on (gate-source voltage negative), NMOS is off. Output connected to VCC through PMOS. Output = HIGH.
When input is HIGH: PMOS is off, NMOS is on. Output connected to GND through NMOS. Output = LOW.
CMOS inverters draw negligible static current because one transistor is always off. Power is consumed only during transitions. This is why CMOS is preferred for battery-powered devices. Static power dissipation is microamps; dynamic power depends on switching frequency and capacitance.
Practical Variations
Schmitt trigger inverter: has hysteresis — switches at a higher voltage when rising than when falling. Used on noisy or slowly changing inputs to prevent multiple transitions. The 74HC14 is a hex Schmitt inverter popular for button debouncing and level conversion.
Open-collector inverter: the pull-up Rc is external. Multiple open-collector outputs can be wired together (wired-AND): the node is LOW if any output pulls it low. Used for bus-sharing without additional logic gates.
Buffer/non-inverting driver: two inverters in series equal a non-inverting buffer with high drive strength. Used to drive heavy capacitive loads (long cables, large capacitors in display systems) that would slow a standard gate output.
Building and Testing
Breadboard construction:
- Insert NPN transistor (2N2222 or BC547) with leads identified (EBC from flat face: Emitter, Base, Collector for TO-92 package — verify with datasheet).
- Connect emitter to GND rail.
- Connect 10 kΩ resistor from an input switch to base.
- Connect 2.2 kΩ resistor from VCC (+5V) to collector.
- Connect LED with 330 Ω series resistor from collector to GND (indicator for output).
Test:
- Switch open (input floating or tied to GND via 10 kΩ pull-down): transistor off, LED on (output HIGH).
- Switch closed to VCC: transistor saturates, LED off (output LOW).
If LED stays on regardless of switch state, the transistor may be incorrectly oriented or the Rb value is too high. If LED is always off, check that the base resistor is not open and that the transistor is an NPN (not PNP).