NOR Gate

Part of Boolean Logic and Gates

A universal gate that outputs 1 only when all inputs are 0 — the complement of OR and an alternative basis for building any digital circuit.

Why This Matters

The NOR gate is the universal gate for CMOS logic in the same way NAND is universal for TTL. Like NAND, NOR can implement any Boolean function by itself — NOT, AND, OR, and all complex functions can be derived from NOR-only circuits. This means you can build an entire digital system using a single gate type.

NOR gates are also natural in certain CMOS circuit topologies. The RTL (Resistor-Transistor Logic) NOR gate is the simplest transistor logic gate — two transistors in parallel with a single pull-up resistor. Understanding NOR gives you a complete second set of universal building blocks, and some circuits are more naturally expressed in NOR form.

In a practical digital build, knowing both NAND and NOR universality doubles your options for simplifying circuits and using whatever gate ICs are available.

What a NOR Gate Does

A NOR gate outputs 1 only when all inputs are 0. If any input is 1, the output is 0.

Two-input NOR truth table:

A	B	A NOR B
0	0	1
0	1	0
1	0	0
1	1	0

NOR is “NOT OR” — OR with the output inverted. Boolean notation: Y = NOT(A OR B).

The symbol is an OR gate with a bubble on the output. NOR and NAND are duals of each other: where NAND has 0 only when all inputs are 1, NOR has 1 only when all inputs are 0.

Building NOR from RTL (Resistor-Transistor Logic)

RTL NOR is the simplest transistor gate circuit:

• One pull-up resistor (Rc, typically 640 Ω) from VCC to the common collector node
• Two NPN transistors (Q1, Q2) with collectors both connected to that node
• Emitters both to GND
• Input A drives base of Q1 through a base resistor (Rb, ~470 Ω)
• Input B drives base of Q2 through Rb

If either or both inputs are HIGH, the corresponding transistor saturates, pulling the collector node to near GND (LOW). Only if both inputs are LOW are both transistors off, allowing the pull-up resistor to hold the output HIGH.

This implements NOR directly with just one resistor and two transistors per gate. Add more transistors in parallel for more inputs.

NOR Universality: Deriving Basic Gates

NOT from NOR: tie both inputs of a 2-input NOR to the same signal: Y = NOR(A, A) = NOT(A OR A) = NOT(A)

OR from NOR: OR requires two NOR gates:

1. Gate 1: P = NOR(A, B)
2. Gate 2 (as inverter): Y = NOR(P, P) = NOT(P) = A OR B

AND from NOR (using DeMorgan): AND(A,B) = NOT(NOT-A OR NOT-B)

1. Gate 1: NOT-A = NOR(A, A)
2. Gate 2: NOT-B = NOR(B, B)
3. Gate 3: Y = NOR(NOT-A, NOT-B) = NOT(NOT-A OR NOT-B) = A AND B

Three NOR gates implement AND, just as three NAND gates implement OR.

SR Latch from NOR

Two cross-coupled NOR gates form an active-high SR latch:

• Gate 1: Q = NOR(R, NOT-Q)
• Gate 2: NOT-Q = NOR(S, Q)

Behavior:

• S=1, R=0: Q is forced to 1 (Set)
• S=0, R=1: Q is forced to 0 (Reset)
• S=0, R=0: Q holds previous state
• S=1, R=1: forbidden (both Q and NOT-Q driven to 0, violating complementarity)

The NOR-based SR latch has active-high inputs (asserted high to activate), compared to the NAND-based SR latch which has active-low inputs. The forbidden state differs: in NAND-SR, both inputs low is forbidden; in NOR-SR, both inputs high is forbidden.

NOR SR latches appear in debouncing circuits for mechanical switches and as the core memory cells in simple state machines.

XOR from NOR

XOR can be built from 5 NOR gates:

1. G1 = NOR(A, B)
2. G2 = NOR(A, G1)
3. G3 = NOR(B, G1)
4. Y = NOR(G2, G3) ← Wait, this gives XNOR

For XOR (not XNOR), add a 5th NOR as inverter: 5. Y = NOR(G4, G4) where G4 = NOR(G2, G3)

Or more efficiently, the XOR circuit from NOR is:

1. P = NOR(A, B)
2. Q = NOR(A, P)
3. R = NOR(P, B)
4. Y = NOR(Q, R)

Verify: A=0,B=0: P=1, Q=NOR(0,1)=0, R=NOR(1,0)=0, Y=NOR(0,0)=1. But XOR(0,0)=0. This gives XNOR, so add a final inverter for XOR. Five gates total for XOR.

Duality of NAND and NOR

Every circuit built from NAND gates has a dual circuit built from NOR gates (and vice versa) by applying the duality principle: swap AND↔OR and 0↔1 throughout.

This means:

• A NAND-based circuit for F(A,B,C) corresponds to a NOR-based circuit for the dual function
• The dual of a NAND SR latch (active-low inputs) is a NOR SR latch (active-high inputs)
• The dual of a NAND-based half adder exists as a NOR-based design

In practice, choose NAND if you have TTL ICs (naturally NAND), NOR if you have RTL or certain CMOS families. Both achieve the same computation; only the gate technology differs.

Common NOR ICs

• 7402: quad 2-input NOR, TTL (complement of 7400 NAND)
• 7427: triple 3-input NOR
• CD4001: quad 2-input NOR, CMOS (wide supply range 3–18V)
• CD4025: triple 3-input NOR, CMOS

The CD4001 CMOS NOR gate running at 10–15V has excellent noise margins (3–5V) and is well-suited to industrial and noisy environments where TTL would be marginal.