NAND Gate

Part of Boolean Logic and Gates

The most fundamental gate in practical digital design — a single NAND gate can implement any Boolean function, making it the universal building block of computing.

Why This Matters

The NAND gate is arguably the most important single component in the history of computing. It is the gate that TTL logic naturally implements, it is universal (all other gates derive from it), and it is the basis of the most common logic IC families. The 74xx00 quad-NAND package has sold in the billions.

When you are rebuilding computing from discrete components, NAND gates are your starting material. You can build any circuit — adders, flip-flops, memories, decoders — using only NAND gates. Stocking one type of gate IC simplifies your parts inventory dramatically.

Understanding the NAND gate deeply — its physical implementation, its electrical characteristics, and its universal properties — is the foundation of practical digital construction.

What a NAND Gate Does

A NAND gate outputs 0 only when all inputs are 1. In all other cases it outputs 1. This is the complement of AND.

Two-input NAND truth table:

A	B	A NAND B
0	0	1
0	1	1
1	0	1
1	1	0

The name NAND comes from “NOT AND” — it is AND with the output inverted. In Boolean notation: Y = NOT(A AND B) = NAND(A,B).

The symbol is an AND gate with a circle (bubble) on the output, indicating inversion. In circuit schematics, a bubble always represents logical inversion.

Physical Implementation in TTL

In TTL (Transistor-Transistor Logic), the NAND gate is implemented with a multi-emitter transistor and a totem-pole output stage. The multi-emitter transistor acts like the AND function — if any emitter is pulled low (input = 0), the input transistor is in reverse-active mode and pulls the base of the output transistor low, turning it off and driving the output high.

Only when all inputs (all emitters) are high does the input transistor operate in forward mode and saturate the output transistor, pulling the output low.

This topology produces the NAND function naturally and efficiently. AND would require an additional inverter stage, making NAND cheaper and faster. This is why TTL logic is fundamentally NAND-based.

In discrete transistor implementation (RTL/DTL), build a NAND gate by combining a diode AND network with a transistor inverter:

• Diodes in parallel between inputs and a common node (acts as AND on current)
• Transistor driven from that node (inverts)

Building NAND from Discrete Components (DTL-Style)

Parts: 2 signal diodes, 1 NPN transistor, 1 clamp diode, 3 resistors, +5V supply.

Schematic:

• Input A → anode of D1
• Input B → anode of D2
• Cathodes of D1 and D2 → node J
• Node J → anode of D3 (clamp diode)
• Cathode of D3 → base of NPN transistor Q1
• 5 kΩ resistor from VCC to node J (pull-up)
• 10 kΩ resistor from base to GND
• 2.2 kΩ resistor from VCC to collector (pull-up)
• Emitter to GND
• Output at collector

This is a DTL NAND gate. See the DTL Logic article for detailed analysis of operation.

Multi-Input NAND Gates

NAND gates with more than 2 inputs are common. A 3-input NAND outputs 0 only when all three inputs are 1. A 4-input NAND requires all four inputs to be 1 for the output to go low.

In TTL, a multi-emitter transistor has one emitter per input — adding inputs is as simple as adding emitters. The 7410 is a triple 3-input NAND; the 7420 is a dual 4-input NAND.

For discrete DTL, add one more input diode per additional input. Fan-in is limited by available base drive current — practical DTL NAND gates work well up to 8 inputs.

NAND Gate Timing

A NAND gate does not switch instantaneously. Key timing parameters:

• Propagation delay (low-to-high, tPLH): time from input rising to output going high. For 74LS00: ~8 ns typical.
• Propagation delay (high-to-low, tPHL): time from input falling to output going low. For 74LS00: ~5 ns typical.

These delays accumulate through cascaded gates. A chain of 10 NAND gates adds 50–80 ns of propagation delay. This limits the maximum clock frequency of any synchronous system built from these gates.

For discrete transistor DTL gates, propagation delays are in the range of 10–100 ns depending on transistor speed and capacitance. Clock speeds of 1–10 MHz are achievable with fast small-signal transistors.

NAND Gate Testing

Test a 2-input NAND gate by applying all four input combinations and measuring the output:

A	B	Expected Output
0	0	HIGH (≈VCC)
0	1	HIGH
1	0	HIGH
1	1	LOW (≈0V)

Use a voltmeter, oscilloscope, or LED with series resistor to observe the output. For an LED indicator: LED is on when output is HIGH (logic 1), off when LOW. Connect from output through a 330Ω resistor to GND.

Common faults:

• Output always high: transistor not turning on — check base drive resistor and clamp diode
• Output always low: transistor not turning off — check GND connection and input pull-downs
• Inconsistent behavior: insufficient supply current — check power supply regulation