Multiplexer
Part of Boolean Logic and Gates
A data-selector circuit that routes one of several input signals to a single output based on select inputs — essential for buses, ALUs, and programmable logic.
Why This Matters
A multiplexer (mux) is one of the most versatile combinational building blocks. It solves the fundamental problem of routing: how to select one signal path out of many and connect it to a common output. Every time a CPU selects between the result of an addition or a comparison to write back to a register, a multiplexer makes that selection. Every time a memory bus switches between data from RAM or ROM, a multiplexer (or its equivalent) is involved.
Muxes also serve as universal logic elements — a 4-to-1 mux can implement any Boolean function of 3 variables by programming its data inputs. This makes them the basis of look-up tables (LUTs) in FPGAs.
In discrete construction, a mux allows you to share a single wire (or bus) among multiple sources, reducing wiring complexity significantly.
The 2-to-1 Multiplexer
The simplest mux has 2 data inputs (D0, D1), 1 select input (S), and 1 output (Y).
| S | Y |
|---|---|
| 0 | D0 |
| 1 | D1 |
When S=0, the output follows D0. When S=1, the output follows D1.
Boolean expression: Y = (NOT-S AND D0) OR (S AND D1)
Gate implementation:
- NOT gate: NOT-S
- AND gate 1: NOT-S AND D0
- AND gate 2: S AND D1
- OR gate: output of AND1 OR AND2
Total: 1 NOT, 2 AND, 1 OR = 4 gates.
Physical analogy: a railway switch — one track comes in, two possible tracks go out (or in reverse, two tracks combine into one). The select input controls which track is connected.
The 4-to-1 Multiplexer
A 4-to-1 mux has 4 data inputs (D0–D3), 2 select inputs (S1, S0), and 1 output (Y).
The select inputs form a 2-bit address (00, 01, 10, 11) that selects among the four data inputs.
| S1 | S0 | Y |
|---|---|---|
| 0 | 0 | D0 |
| 0 | 1 | D1 |
| 1 | 0 | D2 |
| 1 | 1 | D3 |
Boolean expression: Y = (NOT-S1 AND NOT-S0 AND D0) OR (NOT-S1 AND S0 AND D1) OR (S1 AND NOT-S0 AND D2) OR (S1 AND S0 AND D3)
This is a sum of 4 minterms — each minterm selects exactly one data input. Gate implementation requires 2 NOT gates, four 3-input AND gates, and one 4-input OR gate.
The 74LS153 is a classic TTL dual 4-to-1 mux IC. The 74LS151 is an 8-to-1 mux with 3 select inputs.
Cascading Muxes for Wider Selection
To build a 16-to-1 mux from 4-to-1 muxes, use a tree:
- First level: four 4-to-1 muxes, each selecting among 4 of the 16 inputs using select bits S1, S0.
- Second level: one 4-to-1 mux selecting among the four first-level outputs using select bits S3, S2.
Total select inputs: 4 bits, selecting among 16 inputs. This is an elegant recursive structure where each level halves the number of paths.
The Demultiplexer (Demux)
The demux is the inverse of a mux: it routes one input to one of several outputs. With 1 data input, 2 select inputs, and 4 outputs, a 1-to-4 demux connects the input to exactly one output depending on the select value.
A decoder with an enable input functions as a demux: the enable input carries the data, and the address inputs select which output receives it.
Mux and demux are used together in time-division multiplexing (TDM): multiple signals share a single transmission line. On the sending end, a mux samples each signal in sequence and sends it over the line. On the receiving end, a demux distributes each sampled value to the correct output. The select inputs of both circuits are driven by a shared counter.
Mux as a Universal Logic Element
A 2^n-to-1 mux can implement any Boolean function of n+1 variables by setting its data inputs appropriately.
For a 4-to-1 mux (n=2), you can implement any 3-variable Boolean function (A, B, C):
- Use A and B as select inputs.
- For each combination of A and B, set the data input Dk to either C, NOT-C, 0, or 1 based on the desired function.
Example: implement majority function (output 1 when 2 or more of A, B, C are 1):
- A=0, B=0: output should be 0 for any C → D0 = 0
- A=0, B=1: output is 1 only when C=1 → D1 = C
- A=1, B=0: output is 1 only when C=1 → D2 = C
- A=1, B=1: output is 1 for any C → D3 = 1
Connect D0=GND, D1=C, D2=C, D3=VCC, S1=A, S0=B, and the mux output implements the majority function without any external logic gates.
This property makes muxes the basis of FPGA look-up tables, where each LUT is a small mux with its data inputs stored in configuration memory cells.
Bus Multiplexing
In a computer system with multiple data sources (RAM, ROM, I/O ports) sharing a common data bus, a mux selects which source drives the bus at any given time. Only one source can drive the bus at once — connecting two sources simultaneously causes bus contention (both try to drive the wire to different voltages, resulting in high current and possible damage).
Tri-state buffers are an alternative to muxes for bus sharing: each source drives the bus through a tri-state buffer, and only one buffer is enabled at a time. The undriven buffers present high impedance (effectively disconnected). This is the standard approach in microprocessor bus architectures.