Junction Formation

Part of Semiconductors

Techniques for creating p-n junctions in semiconductor material through alloying, diffusion, or epitaxy.

Why This Matters

A semiconductor device is defined by its junctions — the boundaries between p-type and n-type regions. How you form those junctions determines device quality, reproducibility, and the range of devices you can make. Mastering junction formation is the central fabrication skill of semiconductor technology.

Three main methods cover the range from primitive-but-functional to precision-industrial: alloy junction (accessible with improvised equipment), diffusion (requires a controlled furnace), and epitaxy (advanced, requiring specialized apparatus). A rebuilding civilization begins with alloy junctions and progresses toward diffusion as process control improves.

Each method produces junctions with different profiles — the distribution of dopant atoms versus depth — which affects device characteristics like breakdown voltage, capacitance, speed, and gain. Understanding the profiles lets you predict and engineer device behavior rather than accepting whatever your process happens to produce.

Alloy Junction Method

Alloy junction formation is the most primitive technique that still produces functional devices. A donor or acceptor metal is melted onto a semiconductor wafer surface. The metal dissolves semiconductor material to form a liquid alloy at the interface. Upon cooling, the alloy recrystallizes as heavily doped semiconductor, creating an abrupt junction.

Process for PNP germanium transistor (the most accessible starting point):

Materials: n-type germanium wafer (0.5-1 mm thick), indium metal (acceptor for germanium), platinum wire or resistance heater, reducing atmosphere (hydrogen or nitrogen), ceramic or quartz boat.

Procedure:

1. Polish wafer surfaces to optical flatness with progressively finer abrasive (finish with 1-µm alumina or cerium oxide). Clean with acetone, then methanol, then distilled water.
2. Cut tiny indium pieces: approximately 0.5 mm diameter, 0.2 mm thick. Uniformity improves device matching.
3. Place wafer in ceramic boat. Place one indium dot precisely in the center of each face.
4. Insert boat into tube furnace. Flow hydrogen or forming gas (5% H2 in N2) to prevent oxidation.
5. Ramp to 530-560°C over 20 minutes. Hold for 2-5 minutes. Indium melts at 156°C; the melt dissolves germanium until equilibrium. Hold time and temperature control junction depth — longer time and higher temperature mean deeper junction.
6. Cool at 2-3°C/minute. Controlled cooling allows proper recrystallization.
7. Remove from furnace. The indium buttons are now alloyed into the wafer.

Quality indicators: Good junctions show clean, bright indium buttons mechanically bonded to the germanium surface. Dull or porous buttons indicate oxidation (reduce in forming gas more thoroughly). Buttons that lifted off indicate insufficient temperature or contamination preventing wetting.

Junction depth measurement: Section the device, polish cross-section, etch with dilute HCl (which reveals grain boundaries and junction regions), and measure under a 10-100× microscope. Target depth: 100-200 µm into a 500 µm wafer, leaving 100-300 µm base.

Diffusion Junction Method

Diffusion creates junctions by heating the semiconductor in an atmosphere containing dopant atoms, which diffuse into the surface. Unlike alloy junctions, diffusion creates a graded profile (concentration decreasing with depth) and allows precise control of junction depth through time and temperature.

Boron diffusion into n-type silicon (creates p-type surface layer for NPN transistor base or p+n diode):

1. Polish and clean silicon wafer (HF etch in 10% hydrofluoric acid removes native oxide).
2. Load wafer into quartz furnace tube. Heat to 950-1100°C.
3. Bubble nitrogen carrier gas through liquid boron tribromide (BBr3) at room temperature. Carrier gas picks up BBr3 vapor and carries it over the wafer.
4. Reaction: BBr3 decomposes at the hot silicon surface, depositing boron. Boron diffuses into silicon.
5. Diffusion time: 30-60 minutes for shallow junction (0.5-2 µm depth), hours for deeper junctions.
6. Remove from furnace. A p-n junction now exists just below the surface.

Alternative dopant sources:

• Boron: BBr3 liquid source, boron trioxide (B2O3) solid source, or boron-doped oxide glass deposited on wafer.
• Phosphorus (n-type): phosphorus oxychloride (POCl3) liquid, or phosphosilicate glass.
• Arsenic, antimony: compounds available as gases or solid sources.

Temperature-time relationship: Diffusion depth follows √(D×t), where D is diffusivity (temperature dependent) and t is time. At 1000°C, boron in silicon: D ≈ 2×10^-14 cm²/s. One hour gives diffusion depth ≈ √(2×10^-14 × 3600) ≈ 0.27 µm. Higher temperature dramatically increases D — 1100°C gives D ≈ 5×10^-13, giving 1.3 µm in one hour.

Junction depth measurement: Apply a spreader to reveal the junction (etch with hot CrO3-HF mixture which etch rate depends on dopant type), then measure the ring radius to calculate junction depth (angle-lapping technique).

Ion Implantation (Advanced)

Ion implantation shoots ionized dopant atoms into semiconductor material with a beam of precisely accelerated ions. The ions penetrate to a depth determined by their energy (typically 10-300 nm for energies of 30-300 keV). This provides the most precise control of doping profiles but requires an ion implanter — complex, expensive, high-voltage equipment.

For early rebuilding, ion implantation is aspirational. Document the principles: an ion source generates the desired dopant ions, a mass separator selects only the right ion species, an accelerator column accelerates them to target energy, and a scanner sweeps the beam across the wafer for uniform dose. After implantation, an anneal at 700-1000°C repairs crystal damage and electrically activates the implanted atoms.

The value of understanding ion implantation is knowing what becomes possible once high-voltage technology and vacuum systems are available. It enables MOSFET fabrication, precisely controlled base regions, and threshold adjustment for integrated circuits.

Metallurgical Junction Quality Factors

Regardless of formation method, junction quality depends on several factors:

Surface cleanliness: Organic contamination prevents proper alloying or diffusion and creates interface states (trap sites) that increase recombination and leakage. The HF etch before diffusion is critical — it removes the native silicon oxide that would otherwise block boron from entering the silicon.

Crystal perfection: Dislocations (line defects in the crystal) propagate through junctions, creating conductive paths that degrade reverse characteristics. Handle wafers carefully; thermal shock during processing creates dislocations.

Oxidation masking: For diffusion, silicon dioxide (SiO2) acts as a diffusion mask — boron diffuses slowly through it, so oxide-covered regions stay n-type while openings in the oxide allow junction formation. This selective diffusion enables multiple junctions in a single wafer, the basis for integrated circuits.

Gettering: Metallic impurities in the wafer degrade junction quality. Gettering is a process that attracts these impurities to a harmless location (back of wafer, or a polysilicon layer) during high-temperature steps, keeping them away from the junction. Phosphorus gettering: a high-dose phosphorus diffusion on the wafer back creates a gettering sink.

Annealing: After alloy junction formation, a low-temperature anneal (200-300°C for 30 minutes) allows impurity redistribution and relieves mechanical stress, often improving device characteristics. Always anneal before packaging.

Keep process logs for every junction formation run: wafer identification, dopant lot, temperature profile, atmospheric conditions, measured parameters. When a batch produces poor devices, the log tells you what changed. Without logs, troubleshooting is guesswork.