Full Adder

Part of Basic Computing

The full adder is the fundamental binary addition circuit — adding three bits (two operands plus carry-in) to produce a sum bit and carry-out, the building block of all multi-bit addition.

Why This Matters

Addition is the most fundamental arithmetic operation: subtraction, multiplication, and division all reduce to addition with some extra logic. Every CPU ever built contains adder circuits. Understanding the full adder means understanding, at the gate level, how a computer adds two numbers.

The full adder is also a perfect teaching circuit: small enough to analyze completely (truth table has only 8 rows), complex enough to illustrate the design process from truth table through gate implementation through hardware construction. A person who has built and tested a 4-bit ripple adder from discrete gates understands digital design more deeply than someone who has only read about it.

Full adders can be constructed on a breadboard in an afternoon and tested with switches and LEDs. The completed circuit works identically to the adder inside any commercial processor — the same Boolean equations, realized in different technology.

Truth Table and Boolean Equations

A full adder adds three 1-bit inputs: A (first operand), B (second operand), and Cin (carry from the previous lower bit). It produces two outputs: Sum (the result bit) and Cout (carry to the next higher bit).

Complete truth table:

A	B	Cin	Sum	Cout
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

Deriving Sum: it is 1 when an odd number of inputs are 1. This is the XOR function: Sum = A XOR B XOR Cin

Deriving Cout: it is 1 when two or more inputs are 1 (majority function): Cout = (A AND B) OR (A AND Cin) OR (B AND Cin)

This can be simplified by factoring: Cout = A·B + Cin·(A XOR B)

The form Cout = A·B + Cin·(A XOR B) is preferred because (A XOR B) is already computed for Sum, allowing gate sharing.

Gate-Level Implementation

Two-XOR implementation (most common):

1. Half adder 1: Sum1 = A XOR B; Cout1 = A AND B
2. Half adder 2: Sum = Sum1 XOR Cin; Cout2 = Sum1 AND Cin
3. Final carry: Cout = Cout1 OR Cout2

Component count: 2 XOR gates, 2 AND gates, 1 OR gate = 5 gates total.

NAND-only implementation (9 NAND gates, derived earlier in the Boolean algebra section):

1. G1 = NAND(A, B)
2. G2 = NAND(A, G1)
3. G3 = NAND(B, G1)
4. G4 = NAND(G2, G3) — gives A XOR B
5. G5 = NAND(G4, Cin)
6. G6 = NAND(G4, G5)
7. G7 = NAND(Cin, G5)
8. Sum = NAND(G6, G7) — gives Sum
9. Cout = NAND(G1, G5)

With a 74HC00 (quad NAND), you need 3 chips (12 NAND gates available, 9 needed) for one full adder.

With dedicated ICs: 74HC283 is a complete 4-bit fast adder in one package.

Building a 4-Bit Ripple Adder

A ripple-carry adder chains four full adders: the Cout of bit 0 feeds the Cin of bit 1, Cout of bit 1 feeds Cin of bit 2, and Cout of bit 2 feeds Cin of bit 3. The final Cout is the carry out of the 4-bit addition.

The name “ripple-carry” comes from the propagation of carry: in the worst case (all bits 1+1), the carry must ripple through all stages sequentially before the final output settles. This introduces propagation delay proportional to the number of stages.

For 4 bits with 5 ns gate delay per stage and 2 gate delays per carry stage: maximum delay = 4 × 2 × 5 ns = 40 ns. A 4-bit ripple adder settles within 40 ns, corresponding to a maximum clock frequency of 1/40ns = 25 MHz (with margin). For hand-built circuits with slower logic families, actual delays are much longer — but still fast enough for early systems.

Breadboard construction:

• Power: +5V and GND rails
• Input switches: 8 SPDT switches (4 per operand) with 10kΩ pull-down resistors
• Carry-in switch: one additional SPDT switch
• Logic: using 74HC86 (XOR), 74HC08 (AND), 74HC32 (OR)
• Output: 4 LEDs with 330Ω resistors for Sum bits + 1 LED for Cout
• Wire carry chain explicitly: Cout of stage 0 to Cin of stage 1, etc.

Testing: set all known input combinations (00+00 through 15+15 in hex), verify outputs against expected values. The full truth table has 2^9 = 512 rows; verify at least boundary cases, powers of 2, and all-ones inputs.

Half Adder vs. Full Adder

A half adder adds only two bits (no carry-in): Sum = A XOR B; Cout = A AND B. Only 2 gates. Useful only for the least significant bit of a multi-bit adder where Cin = 0, or for isolated single-bit addition.

For any multi-bit adder, only the first stage (LSB) can use a half adder; all other stages require full adders to accept the carry from the previous stage. In practice, using full adders throughout is simpler — just tie Cin of stage 0 to ground (logic 0) unless implementing subtraction, where Cin=1 is needed.

The full adder’s elegance is that one simple circuit, replicated and chained, handles addition of arbitrarily large numbers. This scalability is the key insight: hardware complexity grows linearly with word width, not exponentially.