Decoder

Part of Boolean Logic and Gates

Combinational circuits that translate a binary code into individual signal lines, enabling memory addressing and instruction dispatch.

Why This Matters

A decoder is one of the most useful building blocks in digital systems. It takes a binary number and asserts exactly one output line corresponding to that value. A 3-bit decoder, for example, converts the number 5 (101 in binary) into a signal on output line 5 while all other outputs remain inactive.

Decoders are essential for memory systems: to access byte number N in a RAM array, a decoder selects the correct row and column from N’s binary representation. They are equally essential in CPUs: the instruction decoder examines the opcode bits and enables the correct functional unit to execute that instruction.

In relay or discrete-transistor logic, decoders let you build multiplexed displays, address multiple peripheral devices with a small number of control lines, and implement lookup tables in hardware.

The 2-to-4 Decoder

The simplest practical decoder has 2 input bits (A1, A0) and 4 output lines (Y0–Y3). Exactly one output is active (high) for each of the four possible input combinations.

Truth table:

A1	A0	Y0	Y1	Y2	Y3
0	0	1	0	0	0
0	1	0	1	0	0
1	0	0	0	1	0
1	1	0	0	0	1

Boolean expressions:

• Y0 = NOT-A1 AND NOT-A0
• Y1 = NOT-A1 AND A0
• Y2 = A1 AND NOT-A0
• Y3 = A1 AND A0

Each output is an AND gate with two inputs, using the inverted or non-inverted version of each address bit. Build with two inverters and four 2-input AND gates (10 gates total for the 2-to-4 decoder).

For active-low outputs (more common in TTL systems where outputs are driven low to select), replace AND gates with NAND gates and invert the logic: the selected output goes low, all others stay high.

The 3-to-8 Decoder

A 3-bit decoder has 8 output lines. Each output corresponds to one of the 8 possible 3-bit input values.

Boolean expressions follow the pattern:

• Y0 = NOT-A2 AND NOT-A1 AND NOT-A0
• Y1 = NOT-A2 AND NOT-A1 AND A0
• …
• Y7 = A2 AND A1 AND A0

Each output requires a 3-input AND gate. With three inputs, build from three inverters and eight 3-input AND gates.

The 3-to-8 decoder is commonly used for memory chip select: a computer with eight memory chips uses 3 address lines through a decoder to select which chip responds to the current address. The remaining address lines go directly to all chips to select the byte within the selected chip.

Enable Inputs and Chip Select

Most decoder ICs include one or more enable inputs. When enable is inactive (typically active-low, so EN = 1 means disabled), all outputs are inactive regardless of the address inputs.

The enable input serves as a chip select: it allows multiple decoders to be used together to decode larger addresses. A 4-to-16 decoder can be built from two 3-to-8 decoders: use bit A3 to enable one decoder (A3 = 0) and disable the other (A3 = 1), and pass A2, A1, A0 to both decoders. The low-half decoder handles addresses 0–7, the high-half handles 8–15.

Enable inputs also let decoders function as demultiplexers. By driving the enable input with a data signal while holding the address constant, the data signal appears on the selected output line and is blocked from all others.

BCD-to-7-Segment Decoder

A specialized decoder used for numeric displays is the BCD (Binary Coded Decimal) to 7-segment decoder. A 7-segment LED display has seven independently controlled segments (a through g) arranged to display digits 0–9.

The decoder takes a 4-bit BCD input (0000–1001 for digits 0–9) and drives each segment on or off to form the correct digit shape.

For example, digit 1 requires only segments b and c; digit 8 requires all seven segments. The Boolean expression for each segment output is a function of the four BCD input bits, implemented with gates or read from a ROM.

Building a BCD decoder from gates requires about 20–30 gates per segment, or 140–210 gates total — feasible with a small number of IC packages. The 7447 TTL IC implements this decoder in a single package. Alternatively, a small ROM (16 locations × 7 bits) stores the segment patterns and serves as the decoder.

Decoder as a Minterm Generator

A decoder with n inputs and 2^n outputs generates all possible minterms of the n variables. By OR-ing selected decoder outputs together, you can implement any Boolean function of n variables with a decoder plus one OR gate.

This is an alternative to Karnaugh map minimization: instead of optimizing the gate structure, accept a slightly larger circuit that uses the decoder as a universal function generator. For prototyping and ROM-based lookup tables, this approach is often faster to build than a custom gate array.

A 4-to-16 decoder plus a 16-input OR gate (or several smaller OR gates in a tree) can implement any 4-variable Boolean function. Replace the OR gate with a programmable connection (switches or fusible links) and you have a simple programmable logic array.