D Flip-Flop
Part of Boolean Logic and Gates
A clocked memory element that captures and holds one bit of data on a clock edge — the primary storage cell in digital systems.
Why This Matters
Flip-flops are the fundamental memory cells of digital logic. Every register in a CPU, every bit of state in a state machine, every stage of a shift register — all are built from flip-flops. The D (Data or Delay) flip-flop is the most commonly used type because of its simplicity: one input, one output, and a clock.
Unlike a latch, which is level-sensitive (output follows input while clock is high), a flip-flop is edge-triggered (output changes only at the clock transition). This edge-sensitivity is what makes synchronous digital design predictable: state changes happen at precisely defined moments, not continuously.
In a civilization rebuild, D flip-flops are the primitive you build everything else from — registers, counters, shift registers, state machines. Knowing how to construct one from NAND gates and how it behaves under all conditions is foundational to digital design.
How a D Flip-Flop Works
A positive-edge-triggered D flip-flop has three signals: D (data input), CLK (clock), and Q (output, with NOT-Q as the complement).
Behavior:
- When the clock rises from 0 to 1 (rising edge): Q takes the value of D at that instant.
- At all other times: Q holds its previous value, regardless of what D does.
This is the “sample and hold” behavior. On the clock’s rising edge, the flip-flop takes a snapshot of D and holds it stable until the next rising edge.
If D = 1 just before the clock rises, Q becomes 1 and stays 1 until the next clock edge sets it to whatever D is then. If D = 0 just before the clock rises, Q becomes 0.
The characteristic equation is: Q(next) = D.
Internal Construction from NAND Gates
A D flip-flop is constructed from two SR latches. The first stage is a master SR latch, the second is a slave SR latch. Together they form the master-slave architecture that achieves edge-triggering.
An SR latch is built from two cross-coupled NAND gates:
- Gate 1: output Q = NAND(S, NOT-Q)
- Gate 2: output NOT-Q = NAND(R, Q)
To build a D flip-flop from NAND gates (6 NAND gates total for edge-triggered version):
- Input conditioning: derive S and R from D and NOT-D (D drives S, NOT-D drives R via a NAND inverter).
- Master latch: enabled (transparent) when CLK = 0.
- Slave latch: enabled (transparent) when CLK = 1.
During CLK = 0: master is transparent, capturing D. Slave is opaque, holding previous Q. On CLK rising edge: master becomes opaque (freezes captured value). Slave becomes transparent, transferring master output to Q.
The transition at the clock edge is brief — the slave captures the master’s state before D can change in response to the clock. This is the essential mechanism of edge-triggering.
Timing Parameters
Setup time (Tsu): D must be stable for this long before the clock edge. Violating setup time risks metastability — the flip-flop may settle to an unpredictable state.
Hold time (Th): D must remain stable for this long after the clock edge. Typically shorter than setup time, sometimes near zero for modern gates.
Propagation delay (Tpd): time from clock edge to when Q is valid. The new Q is not reliable until this time after the clock.
Maximum clock frequency: fmax = 1 / (Tpd + Tsu + routing delay). For discrete transistor flip-flops, this might be a few MHz. For CMOS logic ICs, tens to hundreds of MHz.
When building synchronous systems, ensure all combinational paths complete within the clock period minus setup time. The combinational logic between flip-flop stages must produce a stable result before the next clock edge samples it.
Practical D Flip-Flop Circuits
Toggle mode: connect NOT-Q to D. The flip-flop toggles its output on each clock edge. This is a divide-by-2 circuit — the output frequency is half the clock frequency. Essential for building counters.
Shift register: connect Q of one flip-flop to D of the next. On each clock edge, data shifts one stage to the right. An 8-bit shift register stores 8 bits that shift through one position per clock. Used for serial-to-parallel conversion, delay lines, and pseudo-random number generators.
Data register: load a value by setting D inputs to the desired values and pulsing the clock. The register holds the loaded value until the next clock pulse. N flip-flops form an N-bit register.
Latch enable: to make a D flip-flop level-sensitive (transparent when enable = 1), replace the clock input with an enable signal combined with the clock: effective clock = CLK AND Enable. When Enable = 0, the flip-flop ignores the clock and holds its state.
Reset and Preset Inputs
Most flip-flop ICs include asynchronous set (preset) and reset (clear) inputs that override the clock:
- Asynchronous reset (CLR): forces Q to 0 immediately, independent of clock. Active low in most devices.
- Asynchronous set (PRE): forces Q to 1 immediately, independent of clock. Active low.
To synchronize a digital system at power-on, pulse the CLR input low. All flip-flops reset to 0, giving the system a known starting state. This is power-on reset.
Do not assert both PRE and CLR simultaneously — this creates a forbidden state where both Q and NOT-Q are driven to 1, violating the invariant that Q and NOT-Q are complements.
When designing systems from scratch, wire unused PRE/CLR inputs to their inactive level (usually VCC for active-low inputs) via a pull-up resistor. Floating control inputs pick up noise and can cause spurious resets.