Counter
Part of Boolean Logic and Gates
Sequential circuits that count clock pulses, generating binary sequences used in timing, addressing, and control.
Why This Matters
Counters are among the most fundamental sequential building blocks in digital systems. A program counter in a CPU advances through memory addresses. A timer measures elapsed pulses. A frequency divider slows a clock signal down for human-readable time displays. All of these use counters.
Unlike combinational circuits, counters have state — they remember their current count and increment it on each clock edge. This makes them sequential circuits, which depend on flip-flops to store state between clock cycles.
In a rebuild scenario, a counter built from discrete flip-flops lets you sequence operations, generate timing signals, and cycle through a set of addresses or states without a microcontroller. Counters are the bridge between raw gate logic and meaningful time-sequenced behavior.
The Ripple Counter
The simplest counter is the asynchronous ripple counter (also called a ripple-carry counter). It is built from a chain of T flip-flops (or JK flip-flops wired as toggle flip-flops), where each flip-flop divides its input frequency by 2.
A T flip-flop toggles its output on each rising (or falling) edge of its clock input. Connect the Q output of stage 0 to the clock input of stage 1, Q of stage 1 to clock of stage 2, and so on. Each stage toggles at half the frequency of the previous stage.
With four stages (Q0, Q1, Q2, Q3), the counter cycles from 0000 to 1111 (0 to 15 in binary) and wraps back to 0000 on the next clock pulse. Q0 is the least significant bit (LSB), Q3 is the most significant bit (MSB).
To build a 4-bit ripple counter from D flip-flops, wire each flip-flop in toggle mode: connect NOT-Q to D. Then connect Q to the clock input of the next stage.
The name “ripple” comes from the propagation delay: each stage changes only after the previous stage has changed. The final bit Q3 changes only after the transition has rippled through all four stages. This creates a brief period where intermediate incorrect values appear on the output bits — not a problem for slow clocks, but can cause issues in high-speed applications.
The Synchronous Counter
A synchronous counter clocks all flip-flops simultaneously from the same clock signal. Only the toggle enable inputs differ between stages, implementing the logic for when each bit should toggle.
In a synchronous binary counter:
- Q0 toggles on every clock cycle (always enabled)
- Q1 toggles when Q0 = 1
- Q2 toggles when Q0 AND Q1 = 1
- Q3 toggles when Q0 AND Q1 AND Q2 = 1
The enable conditions detect when all lower bits are 1 (the condition for the next bit to toggle in binary counting). Implement these with AND gates feeding the toggle enable inputs of JK or T flip-flops.
Synchronous counters are faster and glitch-free compared to ripple counters because all bits update simultaneously. The tradeoff is slightly more complex wiring for the enable logic.
Modulo-N Counters
A modulo-N counter counts from 0 to N-1 and then resets to 0. A standard 4-bit binary counter is modulo-16. But you often need other moduli — a mod-10 counter (decade counter) is essential for decimal displays.
Method 1: Synchronous reset. Detect the count value N using a combinational circuit, and use the output to synchronously reset all flip-flops to 0 on the next clock edge.
For a mod-10 counter, detect when count = 10 (binary 1010): AND the Q1 and Q3 outputs (the 1-bits of decimal 10). When both are high, load 0 into the counter on the next clock edge.
Method 2: Asynchronous clear. Detect count N and immediately clear all flip-flops asynchronously. This is simpler to wire but produces a brief glitch at the reset state (the counter momentarily shows N before jumping to 0).
Modulo counters are used for:
- BCD counting: 4-bit decade counter for each decimal digit in a display
- Clock division: a mod-60 counter divides a 1 Hz signal into 1-pulse-per-minute
- Ring counters: mod-N counter for N-state sequencing
Counter Applications
Frequency divider: a mod-2 counter (single toggle flip-flop) divides frequency by 2. Chain four mod-2 counters to divide by 16. Use a mod-5 and a mod-2 in series to divide by 10. Frequency dividers generate slower, derivative clocks from a master oscillator.
Address sequencer: a counter drives the address inputs of a memory chip, reading out stored values in sequence. This is used in lookup-table-based function generators and waveform synthesizers.
Event counter: wire the counter clock to a sensor signal. Each event (button press, encoder tick, light pulse) increments the counter. Read the binary count to determine how many events occurred.
Stopwatch: count pulses from a known-frequency oscillator. At 1 kHz, a 16-bit counter overflows after 65.535 seconds. Decode BCD digits for a numeric display.
Building a 4-Bit Ripple Counter
Parts needed: four D flip-flops (or one quad D flip-flop IC), connecting wire, pull-up resistors if needed.
- Wire each flip-flop in toggle mode: connect NOT-Q to D on each stage.
- Connect an external clock (or push-button through a debouncing circuit) to the clock input of stage 0.
- Connect the Q output of stage 0 to the clock input of stage 1.
- Connect Q of stage 1 to clock of stage 2, and Q of stage 2 to clock of stage 3.
- Connect all clock inputs to the rising or falling edge depending on the flip-flop type (check the datasheet).
- Connect LEDs with current-limiting resistors to Q0, Q1, Q2, Q3.
Press the clock button repeatedly and observe the LEDs increment in binary. After 15 presses, the counter resets to 0000.
Verify each count value against the expected binary sequence: 0000, 0001, 0010, 0011, 0100 (note that Q1 and Q0 change simultaneously on the 4th pulse in a ripple counter — this is the ripple delay in action).