Common Emitter

Part of The Transistor

The primary amplification configuration — high voltage gain with signal inversion.

Why This Matters

The common emitter (CE) amplifier is the workhorse of transistor circuit design. It is the configuration used whenever voltage amplification is the primary goal: radio IF amplifiers, audio preamplifiers, oscillator active stages, logic gate inverters. Understanding it completely — not just how to build one but why each component has its value and what happens when conditions change — makes every subsequent circuit design faster and more reliable.

The CE amplifier inverts the signal and provides voltage gain determined by collector resistance divided by emitter transconductance resistance. This single formula (Av = -RC/re) lets you calculate gain instantly and verify it by measurement. Discrepancies between calculated and measured gain are diagnostic of component errors, poor bias, or parasitic effects — each pointing to a specific fix.

For a rebuilding civilization, the CE stage is the first active amplifier circuit to master after basic transistor testing. Build a verified, working CE stage. Then cascade two for high gain. Then modify bias for different Q-points. Everything more complex is built from this foundation.

Core Operation

In common emitter: emitter is the common (ground-referenced) terminal; input is applied base-to-ground (emitter); output is taken collector-to-ground (emitter).

When the base voltage rises slightly (positive-going signal):

• Base current IB increases
• Collector current IC = hFE × IB increases
• Voltage across RC = IC × RC increases
• Collector voltage VC = Vcc - IC × RC decreases

Input goes up; output goes down. The CE stage is an inverter. The voltage gain is negative.

The gain magnitude: |Av| = ΔVC / ΔVin = (ΔIC × RC) / ΔVBE = (gm × ΔVBE × RC) / ΔVBE = gm × RC

Since gm = IC/VT: |Av| = (IC/VT) × RC = RC/re (where re = VT/IC)

This is the fundamental gain equation. At IC = 1 mA: re = 26 Ω. With RC = 4.7 kΩ: |Av| = 4700/26 = 181.

Why higher IC gives higher gain: Higher IC means lower re (the transconductance resistance). Lower re in the denominator means higher gain. This can be confirmed experimentally: bias the transistor at 0.1 mA (re = 260 Ω, Av = 18) versus 2 mA (re = 13 Ω, Av = 362 with same RC). The tradeoff: higher IC means more power consumption and possibly reduced headroom.

The Bypass Capacitor’s Critical Role

Without the emitter bypass capacitor CE, the AC signal current through the transistor also flows through RE, creating negative feedback that reduces gain:

Av (without CE) = -RC / (RE + re) ≈ -RC/RE for RE >> re

For RE = 1 kΩ and RC = 4.7 kΩ: Av = -4.7. Low but very stable — variation in re (with temperature or transistor swap) barely affects gain.

With CE (shorting RE for AC): Av (with CE) = -RC / re = -181

High gain but more sensitive to IC and transistor variation. This is the tradeoff: stability versus gain.

Partial bypass: For a specific lower gain with better stability than full bypass, partially bypass RE. Use a small unbypassed series resistor R_unbypassed in series with CE:

Av = -RC / (R_unbypassed + re)

Set R_unbypassed = 100 Ω for Av = -4700/126 = -37. This stabilizes gain to approximately ±20% across transistor gain variation, while providing 37× amplification.

Partial bypass is common in IF amplifier stages where gain must be consistent across multiple production units.

Frequency Response

The CE amplifier does not amplify all frequencies equally. Low-frequency response is limited by coupling and bypass capacitors. High-frequency response is limited by transistor capacitances and the Miller effect.

Low-frequency cutoff: Coupling capacitor Cin with source resistance Rs and input impedance Zin forms a high-pass filter. Low-frequency -3dB point: f_L = 1 / (2π × Cin × (Rs + Zin)).

For Cin = 10 µF, Rs = 1 kΩ, Zin = 2.5 kΩ: f_L = 1 / (2π × 10×10^-6 × 3500) = 4.5 Hz. Well below audio range.

Similarly, emitter bypass capacitor CE with RE forms a high-pass filter: f_E = 1 / (2π × CE × (RE || (re + RS/hFE))).

For CE = 100 µF, RE = 1 kΩ, re = 26 Ω, RS/hFE = 10 Ω: f_E ≈ 1 / (2π × 100×10^-6 × 36) ≈ 44 Hz. This is the dominant low-frequency pole. Use CE >> 100 µF to push the cutoff below 20 Hz.

High-frequency rolloff — Miller effect: The collector-base capacitance Cµ (in transistor datasheet, or measured) appears from input to output. Because output is 180° inverted and has voltage gain Av:

C_Miller = Cµ × (1 + |Av|)

For Cµ = 5 pF and |Av| = 100: C_Miller = 505 pF. This large capacitance from base to ground (via Miller multiplication) forms a low-pass filter with source impedance: f_H = 1 / (2π × Rs × C_Miller).

For Rs = 1 kΩ, C_Miller = 500 pF: f_H = 1 / (2π × 1000 × 500×10^-12) = 318 kHz.

To extend high-frequency response: reduce source impedance (emitter follower input stage), reduce gain (lower RC), or choose transistors with lower Cµ. High-frequency transistors (2N918, 2N2369) have Cµ as low as 0.5-1 pF, pushing f_H into the tens of MHz.

Multi-Stage Cascading

Two CE stages in cascade multiply gains: total gain = Av1 × Av2 = 181 × 181 = 32,761. This is more than enough for most applications — a 1 mV microphone signal becomes 32 V, which would clip on a 9V supply. In practice, use less gain per stage or reduce RC.

Inter-stage coupling: The output of stage 1 (collector, DC bias near Vcc/2 = 4.5V) must couple to the base of stage 2 (which needs DC bias at ~1.7V). A coupling capacitor blocks the DC offset while passing the signal. Size it for flat response down to desired low frequency (usually 20 Hz for audio).

Loading effect: Stage 2’s input impedance loads stage 1’s collector resistance. Effective load of stage 1: RC1 || Zin_stage2. For RC1 = 4.7 kΩ and Zin2 = 2.5 kΩ: effective load = 1.67 kΩ. Actual gain of stage 1 is reduced from 181 to 181 × (1.67/4.7) = 64. Account for this in multi-stage gain calculations.

Stagger tuning for bandpass: In IF amplifiers (radio frequency intermediate frequency stages), each CE stage is tuned to slightly different resonant frequencies to achieve a flat bandpass response wider than any single stage. This is the basis of superheterodyne radio receiver IF chains.

Practical Build Checklist

Building a verified CE amplifier stage:

1. Calculate: choose IC, calculate re, choose RC for desired gain, calculate RE (10% of Vcc), bias divider for VB.
2. Assemble on breadboard. Install bypass and coupling capacitors.
3. Power supply check: Vcc stable, ripple < 10 mV.
4. DC check: measure VB, VE, VC. Compare to calculated values. Tolerance ±20% acceptable.
5. Signal injection: apply 10 mV at 1 kHz from audio oscillator (or a tone from a battery-operated buzzer). Measure output across RC with oscilloscope or estimate from voltmeter.
6. Gain check: output/input should match calculated value within ±30%.
7. Clip test: increase input until output clips. Clipping should be symmetric (top and bottom equally) if Q-point is centered.
8. Frequency sweep: check gain at 100 Hz, 1 kHz, 10 kHz. Should be flat within ±3 dB (within factor of 1.4) across range.
9. Document the working circuit: schematic, measured Q-point, measured gain, power supply, transistor type and hFE.

A fully documented, tested CE stage is the reusable design block for all subsequent amplifier work.