Clock Generation

Part of Basic Computing

A clock signal is the heartbeat of a synchronous digital system — a regular square wave that coordinates all sequential operations across the processor.

Why This Matters

Synchronous digital circuits — flip-flops, registers, CPUs — change state only at the edges of a clock signal. Without a clock, combinational logic settles to stable outputs but sequential logic has no coordination: different paths through the circuit take different times, and without synchronization, results arrive at destinations at unpredictable moments, corrupting data.

The clock solves this problem by defining moments when data is “captured” (registered). Between clock edges, signals propagate through combinational logic and settle. At the clock edge, all registers simultaneously latch their inputs. Timing analysis confirms that the slowest path settles before the next clock edge — this is the fundamental timing constraint determining maximum clock frequency.

Building a reliable clock circuit is one of the first steps in constructing any sequential digital system. Understanding clock requirements also means understanding why system timing can fail and how to debug it.

Crystal Oscillators

The most precise and stable clocks use a quartz crystal. A quartz crystal has a mechanical resonant frequency determined by its physical dimensions, which (by the piezoelectric effect) corresponds to an electrical resonant frequency. Typical frequencies: 32.768 kHz (watch crystals, common and inexpensive), 1 MHz to 20 MHz (microprocessor crystals).

Crystal oscillator circuit (Pierce oscillator, simplest implementation):

Components: inverting logic gate (CMOS works well), crystal, two capacitors (C1, C2 ≈ 22pF each), feedback resistor (R ≈ 1MΩ), optional output series resistor (Rs ≈ 100Ω).

Circuit: connect resistor R from inverter output to inverter input (biases the inverter as a linear amplifier). Connect the crystal in series from input to output, with capacitors C1 and C2 to ground at each crystal terminal. The result oscillates at the crystal’s series resonant frequency.

The output is a roughly sinusoidal signal that can be squared up by passing through a second inverter. Output frequency stability: ±50 ppm or better over temperature, far superior to RC oscillators.

Crystals in the 1–10 MHz range are excellent for simple CPUs. Divide down with counters to get slower clock rates for display or peripheral timing.

RC Oscillators

When crystal precision is not required, an RC oscillator is far easier to build from scratch.

CMOS ring oscillator: chain an odd number of inverter stages (3, 5, 7…) end to end. Each stage inverts its input; three in series inverts three times (net inversion). The output is fed back to the input, creating instability: when the output is high, it propagates through the chain and eventually forces itself low, which then forces it high again. The oscillation frequency depends on the propagation delay of each gate.

With discrete CMOS gates (4069 hex inverter), three stages oscillate at roughly 1–10 MHz depending on supply voltage and temperature. Frequency is neither precise nor stable, but adequate for demonstrating sequential circuit behavior.

555 timer astable circuit: the 555 timer in astable mode is the workhorse RC oscillator for experimentation. Circuit:

• Pin 8 to +5V, Pin 1 to GND
• Connect RA (47kΩ) from Pin 8 to Pin 7
• Connect RB (47kΩ) from Pin 7 to Pin 6 (tied to Pin 2)
• Connect C (10µF) from Pin 6 to GND
• Pin 4 (reset) to Pin 8
• Output at Pin 3

Frequency f ≈ 1.44 / ((RA + 2·RB) · C) ≈ 1.44 / (0.141 × 0.00001) ≈ 1,021 Hz ≈ 1 kHz

For 1 Hz (visible LED blink): RA = 1kΩ, RB = 47kΩ, C = 10µF → f ≈ 1.44/(0.095 × 0.00001) ≈ 1.5 Hz approximately. Adjust R and C values for target frequency.

Duty cycle (fraction of time output is high) = (RA + RB) / (RA + 2·RB). For equal RA=RB, duty cycle = 2/3. For 50% duty cycle, RA → 0 and add a diode to bypass RB during charging.

Clock Distribution

A clock signal must reach every register and flip-flop in the system with minimal skew (difference in arrival time between different points). Excessive clock skew causes setup and hold time violations — registers capture wrong data.

For simple hand-built circuits (a few dozen flip-flops), distribute the clock through buffer chains. Use a single inverting or non-inverting buffer driving multiple clock inputs, keeping all traces short and of similar length.

For larger systems, a clock tree is used: the clock drives a root buffer, which drives two branches, each driving two sub-branches, etc. Each leaf drives one register. This fan-out tree keeps delay equal on all paths.

Practical rules for small hand-built systems:

• Keep clock signal wires shorter than data wires
• Do not share clock with other signals in the same wire bundle
• Add a 100Ω series resistor at the clock source to reduce ringing
• Place 100nF decoupling capacitors near every IC’s power pins

Manual Clock and Single-Step Mode

For debugging a hand-built CPU, a manually-controlled clock is indispensable. A single pushbutton with contact debouncing substitutes for the oscillator clock, allowing the builder to step through execution one instruction at a time.

Debouncing circuit with SR latch (using two NAND gates):

• Two NAND gates cross-coupled (NAND1 output to NAND2 input, NAND2 output to NAND1 input)
• NAND1 other input connects to Set (button)
• NAND2 other input connects to Reset (second button terminal or pull-up)
• Output from NAND2 is clean, debounced signal

Alternatively, use a 74HC14 Schmitt trigger with RC input (R=10kΩ, C=100nF): the RC smooths the mechanical bounce, and the Schmitt trigger’s hysteresis generates a clean edge.

For automated single-step mode, use two clock signals: a slow clock (1–10 Hz, visually observable on LEDs) and a fast clock (full speed). A selector switch chooses between them. This lets the builder step slowly through initialization, then switch to full speed for normal operation.

Start every new sequential circuit design with a 1 Hz clock. Confirm correct operation with LEDs before increasing speed. Problems that appear only at high speed are timing violations — the circuit works at low speed because slow clocks give plenty of settling time.