Full Adder

Part of Boolean Logic and Gates

A combinational circuit that adds three bits (two data bits plus carry-in) — the building block for multi-bit binary arithmetic.

Why This Matters

The full adder is the core cell of every binary arithmetic unit. To add two 8-bit numbers, you chain eight full adders in sequence, with the carry output of each stage feeding the carry input of the next. This ripple-carry architecture extends to 16, 32, or 64 bits simply by adding more stages.

Every CPU’s arithmetic-logic unit (ALU) contains adder circuits at its heart. Understanding the full adder — its Boolean equations, its gate implementation, and its cascading behavior — is the key to understanding how computers perform arithmetic at the hardware level.

In a discrete-component build, a 4-bit ripple-carry adder can be assembled from 36 individual gates, demonstrating binary arithmetic in a circuit you can probe with a voltmeter and verify by hand.

The Problem: Adding Three Bits

A half adder handles two bits and produces a sum and carry. But when chaining adders to handle multi-bit numbers, each internal stage must also add the carry-out from the previous stage. That gives three inputs: bit A, bit B, and carry-in (Cin). The full adder handles exactly this three-input addition.

Possible results:

• 0+0+0 = 0, no carry
• 1+0+0 = 1, no carry
• 0+1+0 = 1, no carry
• 0+0+1 = 1, no carry
• 1+1+0 = 2 = binary 10, so sum=0, carry=1
• 1+0+1 = 2, sum=0, carry=1
• 0+1+1 = 2, sum=0, carry=1
• 1+1+1 = 3 = binary 11, so sum=1, carry=1

Truth Table and Boolean Equations

A	B	Cin	Sum	Cout
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

Sum = A XOR B XOR Cin

Cout = (A AND B) OR (Cin AND (A XOR B))

The Sum equation shows that the sum bit is the XOR of all three inputs. XOR is essentially “odd parity” — sum is 1 when an odd number of inputs are 1 (1 or 3), and 0 when an even number are 1 (0 or 2). This matches binary addition.

The Cout equation says a carry is generated when both A and B are 1 (regardless of Cin), or when Cin is 1 and exactly one of A or B is 1 (propagate carry). This is the generate-propagate model of carry logic.

Gate-Level Implementation

Standard implementation using 5 gates:

1. Gate 1: X = A XOR B (intermediate)
2. Gate 2: Sum = X XOR Cin
3. Gate 3: G = A AND B (generate)
4. Gate 4: P = X AND Cin (propagate)
5. Gate 5: Cout = G OR P

This requires 2 XOR gates, 2 AND gates, and 1 OR gate.

Alternative implementation using only NAND gates (9 NAND gates):

• XOR from 4 NAND gates
• AND from 2 NAND gates plus an inverter
• OR from 3 NAND gates (using DeMorgan)

The NAND-only implementation is useful when building from a single IC type (e.g., a 74xx00 quad-NAND package).

Building a 4-Bit Ripple-Carry Adder

Four full adders in cascade add two 4-bit numbers A[3:0] and B[3:0].

Connections:

• Stage 0 (LSB): A0, B0, Cin=0 → Sum0, Cout0
• Stage 1: A1, B1, Cin=Cout0 → Sum1, Cout1
• Stage 2: A2, B2, Cin=Cout1 → Sum2, Cout2
• Stage 3 (MSB): A3, B3, Cin=Cout2 → Sum3, Cout3

The final Cout3 is the carry-out of the 4-bit addition — it goes high if the result exceeds 15 (1111). This is the overflow bit.

Total gate count for 4-bit ripple adder: 4 × 5 = 20 gates minimum, or 4 × 9 = 36 NAND gates.

Propagation delay: each stage must wait for the carry to arrive before its output is valid. In a 4-bit ripple adder, the worst case is when the carry must ripple through all four stages (e.g., adding 0111 + 0001 produces 1000, where carry ripples from bit 0 to bit 3). The worst-case delay is 4 × (stage delay). For longer adders, this ripple delay becomes significant.

Testing and Verification

Wire up input switches for A[3:0] and B[3:0] (8 switches total). Connect outputs Sum[3:0] and Cout to LEDs.

Test cases:

• 0101 (5) + 0011 (3) = 1000 (8), no carry out
• 1111 (15) + 0001 (1) = 10000 → Sum=0000, Cout=1
• 0110 (6) + 0111 (7) = 1101 (13), no carry out
• 1010 (10) + 1010 (10) = 10100 → Sum=0100 (4), Cout=1

Use a calculator to verify binary arithmetic, then check each LED matches. If errors occur, probe intermediate carry signals to isolate which stage is faulty.